Senior AI Chip Verification Architect - Flexible PTO

Persimmons, Inc.; San Jose (CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Competitive salary & benefits

Flexible PTO

401k

Résumé du poste

Persimmons, Inc. is building AI hardware infrastructure and seeks a founding Senior ASIC Design Verification Engineer to own the verification of the AI Persimmons inference chiplet, coordinating with design, algorithm and compiler teams to ensure silicon aligns with specifications and is free of critical bugs before tape-out.

You will lead test plan development, build portable UVM testbenches, drive coverage, validate C/C++ firmware on RISC-V cores, and extend verification with FPGA prototyping

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.

Responsabilités

• Lead verification planning and execution from subsystem to full chip, collaborating with CTO, design and software teams.
• Design and implement UVM testbenches with constrained-random stimulus and scoreboards.
• Drive coverage closure using code, functional, and formal coverage; apply formal verification where effective.
• Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
• Extend verification with FPGA prototyping on Synopsys HAPS for real workloads.
• Use AI agents to attack verification tasks like testbench generation and regression triage.
• Run efficient regressions to converge bugs early and optimize license usage.

Connaissances

SystemVerilog/Verilog

UVM

C/C++ embedded

RISC-V

Verification leadership

Formation

Electrical/Computer Engineering degree

Outils

Synopsys HAPS

Description du poste

Persimmons, Inc. is building AI hardware infrastructure and seeks a founding Senior ASIC Design Verification Engineer to own the verification of the AI Persimmons inference chiplet, coordinating with design, algorithm and compiler teams to ensure silicon aligns with specifications and is free of critical bugs before tape-out.

You will lead test plan development, build portable UVM testbenches, drive coverage, validate C/C++ firmware on RISC-V cores, and extend verification with FPGA prototyping