Lead AI ASIC Verification Engineer – Onsite in San Jose

Persimmons; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Competitive salary and benefits

Flexible PTO

401k

Job summary

Persimmons is seeking a founding Senior ASIC Design Verification Engineer in San Jose to own verification of the AI Persimmons inference chiplet. You will partner with design, algorithm, and compiler teams to ensure silicon meets specs and is bug-free before tape-out.

You will lead verification planning, build portable UVM testbenches, develop firmware tests on RISC-V, and drive coverage closure with formal methods and AI-assisted workflows. On-site work required in San Jose.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• 5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
• Verification experience on compute and fabric datapaths.
• Advanced SystemVerilog/Verilog and UVM, plus C/C++ embedded code development and validation on RISC-V or similar processors.
• A track record of scalable verification flows, coverage-driven strategies, assertion-based and formal verification, and data-driven decisions.
• Experience with AI-driven workflows and automation for regression triage, log analysis, or testbench generation.
• Startup-ready: comfortable leading a small, high-ownership team and working on site in San Jose.

Responsibilities

• Lead verification planning and execution from subsystem to full chip, collaborating with CTO, design and software teams.
• Design and implement UVM testbenches with constrained-random stimulus, compute reference models, and portable scoreboards.
• Drive coverage closure using code, functional, and formal coverage; apply formal verification where effective.
• Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
• Extend verification with FPGA prototyping on Synopsys HAPS to run small real workloads.
• Use AI agents to attack testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
• Run efficient, automated regressions to conserve EDA licenses and drive bugs to closure.

Skills

Test planning

Debugging

Leadership

Problem solving

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

SystemVerilog/Verilog

UVM

C/C++ embedded

RISC-V

Job description

Persimmons is seeking a founding Senior ASIC Design Verification Engineer in San Jose to own verification of the AI Persimmons inference chiplet. You will partner with design, algorithm, and compiler teams to ensure silicon meets specs and is bug-free before tape-out.

You will lead verification planning, build portable UVM testbenches, develop firmware tests on RISC-V, and drive coverage closure with formal methods and AI-assisted workflows. On-site work required in San Jose.