Senior ASIC Verification Engineer - Remote & Equity

Positron Corporation; United States; Remote; USD 200,000 - 350,000; Full time

Benefits offered by this job

Equity

Flexible remote work

Comprehensive benefits

Job summary

Positron AI seeks an ASIC Design Verification Engineer to lead advanced verification for AI inference ASICs. You will define verification strategies, build robust testbenches, and drive coverage closure across pre- and post-silicon stages.

The role requires 8+ years in ASIC verification, SystemVerilog UVM expertise, and strong collaboration with design and software teams. Remote-friendly, with a competitive package.

Qualifications

• 8+ years of experience in ASIC verification.
• Advanced degree in Electrical or Computer Engineering or related field.
• Hands-on debugging, waveform analysis, and scripting skills.
• Familiarity with AI/ML accelerators and high-speed interconnects.

Responsibilities

• Develop and execute verification strategies for AI inference ASICs.
• Define and implement comprehensive test plans and verification methodologies.
• Lead verification environments using SystemVerilog UVM.
• Create and maintain simulation testbenches with directed and constrained-random tests.
• Collaborate with design/architecture to ensure coverage and closure.
• Drive debugging and root-cause analysis in pre/post-silicon validation.
• Coordinate with FPGA and emulation teams for early validation.
• Manage verification schedules, deliverables, and risk mitigation.

Skills

SystemVerilog UVM

Verification planning

Testbench development

Coverage-driven verification

Debugging tools

Waveform analysis

Scripting (Python, Perl, TCL)

AI accelerators familiarity

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Cadence

Synopsys

Mentor Graphics

Job description

Positron AI seeks an ASIC Design Verification Engineer to lead advanced verification for AI inference ASICs. You will define verification strategies, build robust testbenches, and drive coverage closure across pre- and post-silicon stages.

The role requires 8+ years in ASIC verification, SystemVerilog UVM expertise, and strong collaboration with design and software teams. Remote-friendly, with a competitive package.