Senior ASIC Design Verification Engineer (AI Compute)

Persimmons; San Jose (CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Competitive salary and benefits

Flexible PTO

401k

Résumé du poste

Persimmons is seeking a founding Senior ASIC Design Verification Engineer in San Jose to own verification of the AI Persimmons inference chiplet. You will partner with design, algorithm, and compiler teams to ensure silicon meets specs and is bug-free before tape-out.

You will lead verification planning, build portable UVM testbenches, develop firmware tests on RISC-V, and drive coverage closure with formal methods and AI-assisted workflows. On-site work required in San Jose.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• 5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
• Verification experience on compute and fabric datapaths.
• Advanced SystemVerilog/Verilog and UVM, plus C/C++ embedded code development and validation on RISC-V or similar processors.
• A track record of scalable verification flows, coverage-driven strategies, assertion-based and formal verification, and data-driven decisions.
• Experience with AI-driven workflows and automation for regression triage, log analysis, or testbench generation.
• Startup-ready: comfortable leading a small, high-ownership team and working on site in San Jose.

Responsabilités

• Lead verification planning and execution from subsystem to full chip, collaborating with CTO, design and software teams.
• Design and implement UVM testbenches with constrained-random stimulus, compute reference models, and portable scoreboards.
• Drive coverage closure using code, functional, and formal coverage; apply formal verification where effective.
• Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
• Extend verification with FPGA prototyping on Synopsys HAPS to run small real workloads.
• Use AI agents to attack testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
• Run efficient, automated regressions to conserve EDA licenses and drive bugs to closure.

Connaissances

Test planning

Debugging

Leadership

Problem solving

Formation

Bachelor's or Master's in Electrical/Computer Engineering

Outils

SystemVerilog/Verilog

UVM

C/C++ embedded

RISC-V

Description du poste

Who we are

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, we're on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn't imagined yet.

Why join us

We're growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact, we want to talk to you.

What you'll do

As a founding Senior ASIC Design Verification Engineer, you will own verification of the AI Persimmons inference chiplet, that runs the smallest to largest AI models. You will partner daily with the design, algorithm and compiler teams to make sure silicon matches its intended feature set and is free of critical bugs before tape-out. Your primary duties and responsibilities include:

• Lead verification planning and execution from subsystem to full chip. Collaborate with the CTO, design and software teams to build test plans that validate implementation against specifications with no significant gaps.
• Design and implement UVM testbenches with constrained-random stimulus, compute reference models, and scoreboards that stay portable from subsystem to chip level and are built for fast debugging.
• Drive coverage closure using code, functional, and formal coverage, applying formal verification where it is most effective in the compute logic.
• Develop and validate C/C++ firmware tests running on RISC-V cores to exercise compute features end to end.
• Extend verification with FPGA prototyping on Synopsys HAPS, enabling software teams to run small real workloads.
• Use AI agents to attack the highest-cost parts of verification: testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
• Run efficient, automated regressions that conserve EDA licenses, analyze bug trends, and systematically drive bugs to closure, with a passion for finding them early.

What You Bring To The Table:

• Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Proven Experience: 5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
• Compute Expertise: Verification experience on compute and fabric datapaths.
• Technical Mastery: Advanced SystemVerilog/Verilog and UVM, plus C/C++ embedded code development and validation on RISC-V or similar processors.
• Verification Leadership: A track record of scalable verification flows, coverage-driven strategies, assertion-based and formal verification, and data-driven calls on what to cut and what is non-negotiable before tape-out.
• AI-Driven Workflows: You have built real AI-driven workflows, not just chatted with a model. You've written instructions for agents and shipped automation, ideally for regression triage, log analysis, or testbench generation.
• Startup Ready: Comfortable leading and being hands-on in a small, high-ownership team, staying calm under pressure, and working on site in San Jose.
• Competitive salary and benefits package
• Flexible PTO
• 401k