Lead ASIC Architect for AI Inference SoCs

Positron AI; Austin (TX); On-site; USD 225,000 - 350,000; Full time

Benefits offered by this job

Competitive salary + equity

Flexible work environment

Career growth opportunities

Job summary

Positron AI in Austin, Texas, is seeking a Principal ASIC Design Engineer to lead IP blocks and subsystems for inference ASICs/SoCs, owning microarchitecture from concept to RTL signoff and mentoring junior engineers.

You will define microarchitecture, deliver production-grade SystemVerilog RTL, drive PPA improvements, collaborate across architecture, verification, and PD, and contribute automation and signoff checklists. This role offers a competitive package and growth opportunities.

Qualifications

• 8+ years of ASIC/SoC RTL design experience.
• Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.
• Deep SystemVerilog RTL expertise, including clocking and CDC/RDC handling.
• Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT).
• Hands-on experience with multiple interfaces (HBM/DDR, PCIe/CXL, AXI/ACE/CHI).
• Strong cross-functional communication and collaboration skills.

Responsibilities

• Define and document microarchitecture for complex IP blocks/subsystems.
• Deliver production-quality, parameterized SystemVerilog RTL with defined interfaces and embedded assertions.
• Lead lint, CDC/RDC, DFT integration and synthesis bring-up; collaborate with PD on floorplan and timing closure.
• Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
• Architect and integrate high-performance interconnects and memory interfaces (HBM/DDR, PCIe/CXL).
• Develop guidelines, packaging, and signoff checklists; mentor junior engineers.
• Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.
• Partner with Verification to define test plans and reference models; support bring-up and customer engagements.
• Lead design reviews and advocate for best-in-class solutions; drive tradeoffs with architectures.

Skills

ASIC/SoC RTL design

SystemVerilog RTL

Leadership and mentoring

Front-end flows

Memory interfaces

Education

BS/MS in EE/CE (or related)

Tools

HBM/DDR

PCIe/CXL

AMBA AXI/ACE/CHI

Cache/memory hierarchies

High-throughput datapaths

Job description

Positron AI in Austin, Texas, is seeking a Principal ASIC Design Engineer to lead IP blocks and subsystems for inference ASICs/SoCs, owning microarchitecture from concept to RTL signoff and mentoring junior engineers.

You will define microarchitecture, deliver production-grade SystemVerilog RTL, drive PPA improvements, collaborate across architecture, verification, and PD, and contribute automation and signoff checklists. This role offers a competitive package and growth opportunities.