RTL Design Engineer for AI Inference ASIC — Full Ownership

Acceler8 Talent; Palo Alto (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Acceler8 Talent is seeking an experienced RTL Design Engineer to help build a next-generation AI accelerator for LLM inference. You will own RTL development across blocks, from architectural concepts to tapeout, shaping microarchitecture, verification, and timing in a hands-on role.

You will translate high-level specs into synthesizable RTL, optimize datapaths, and collaborate with verification and physical design teams to meet stringent PPA targets.

Qualifications

• Extensive hands-on RTL development for ASIC/SoC with ownership of blocks from concept to tapeout.
• Strong proficiency in Verilog/SystemVerilog and digital design fundamentals.
• Proven ability to optimize power, performance, and area across the design flow.

Responsibilities

• Translate architectures into detailed RTL and microarchitectures.
• Design and optimize datapaths, control logic, and interfaces.
• Work with verification and physical teams to close timing and integration issues.
• Own design blocks end-to-end through integration and tapeout readiness.

Skills

ASIC RTL

SystemVerilog

Verilog

Digital design

PPA optimization

Synthesis

STA

Tapeout experience

Job description

Acceler8 Talent is seeking an experienced RTL Design Engineer to help build a next-generation AI accelerator for LLM inference. You will own RTL development across blocks, from architectural concepts to tapeout, shaping microarchitecture, verification, and timing in a hands-on role.

You will translate high-level specs into synthesizable RTL, optimize datapaths, and collaborate with verification and physical design teams to meet stringent PPA targets.