Architect

Acceler8 Talent; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent seeks an experienced Chip Architect to translate architectural concepts into detailed microarchitecture for a next-generation LLM inference ASIC. You will collaborate with RTL, verification, and physical design to ensure architectural decisions become efficient silicon.

You will own critical trade-offs across compute, memory, interconnect, and data movement, optimizing for throughput, latency, power, and area, and influence future silicon generations.

Qualifications

• Extensive ASIC/SoC architecture experience with ownership of hardware design decisions.
• Strong understanding of digital hardware architecture and implementation
• Deep expertise in compute architectures, memory hierarchies, interconnects and data movement.
• Proven ability to translate architectural concepts into implementable microarchitecture.
• Experience evaluating throughput, latency, power, performance and area trade-offs.
• Experience working with RTL, verification and physical design teams.

Responsibilities

• Translate high-level inference requirements into chip and block-level microarchitecture specs.
• Develop and refine architectural decisions across compute, memory, interconnects and data movement.
• Evaluate trade-offs involving throughput, latency, power, performance and area (PPA).
• Collaborate with RTL engineers to translate requirements into hardware implementations.
• Work with design verification and physical design teams to resolve constraints.
• Analyze performance bottlenecks using quantitative data to drive changes.
• Evaluate workload characteristics to optimize inference performance.
• Support first-generation silicon development and tapeout readiness.
• Identify architectural limitations and opportunities for improvement.
• Help define direction for future-generation inference accelerators.

Skills

ASIC/SoC architecture

microarchitecture ownership

RTL impact on architecture

verification collaboration

physical design collaboration

compute architectures

memory hierarchy

interconnects

data movement

PPA trade-offs

Job description

An early-stage, venture-backed AI semiconductor startup is seeking an experienced Chip Architect to help develop a next-generation ASIC purpose-built for large language model (LLM) inference.

The company is building a specialized AI accelerator and supporting software stack, offering the opportunity to contribute directly to its first generation of silicon while shaping the architecture of future chip generations.

The initial architecture is largely defined, so this role focuses on translating architectural concepts into implementable microarchitecture, resolving complex engineering trade-offs, and optimizing the design for real-world inference workloads.

You'll work closely with RTL, design verification, and physical design engineers to ensure architectural decisions translate into efficient, high-performance silicon.

Key Responsibilities

• Translate high-level inference system requirements into detailed chip and block-level microarchitecture specifications.
• Develop and refine architectural decisions across compute, memory hierarchy, interconnects, and data movement.
• Evaluate trade-offs involving throughput, latency, power, performance, and area (PPA).
• Collaborate with RTL engineers to translate architectural requirements into efficient hardware implementations.
• Work closely with design verification and physical design teams to identify and resolve implementation constraints.
• Analyze performance bottlenecks and use quantitative data to drive architectural improvements.
• Evaluate workload characteristics and hardware utilization to optimize inference performance.
• Support first-generation silicon development, including design integration, implementation trade-offs, and tapeout readiness.
• Identify architectural limitations and opportunities for improvement based on implementation feedback.
• Help define the technical direction and architectural evolution of future-generation inference accelerators.

Required Qualifications

• Extensive experience in ASIC/SoC architecture or microarchitecture, with demonstrated ownership of significant hardware design decisions.
• Strong understanding of digital hardware architecture and the implementation challenges associated with complex semiconductor designs.
• Deep expertise in compute architectures, memory hierarchies, interconnects, and data movement.
• Proven ability to translate architectural concepts into detailed, implementable microarchitecture.
• Experience evaluating hardware trade-offs involving throughput, latency, power, performance, and area.
• Strong understanding of how architectural decisions affect RTL implementation, verification, and physical design.
• Ability to analyze complex hardware performance bottlenecks and develop quantitative, evidence-based solutions.
• Demonstrated experience collaborating with RTL, verification, and physical design engineering teams.
• Staff-to-Principal-level technical depth, with a strong desire to remain hands-on in architecture development and engineering problem-solving.

Preferred Qualifications

• Experience architecting AI accelerators, inference ASICs, GPUs, or other high-performance compute processors.
• Familiarity with LLM inference workloads and specialized machine learning accelerator architectures.
• Experience with performance modeling, workload characterization, and architecture exploration.
• Knowledge of memory bandwidth optimization, compute utilization, and efficient data movement.
• Experience taking semiconductor architectures from initial design through RTL implementation, physical closure, and tapeout.
• Involvement in successful ASIC/SoC tapeouts and post-silicon performance analysis.
• Background developing first-generation silicon or working within early-stage semiconductor startups.

Why Join?

• Help develop a next-generation LLM inference accelerator from the ground up.
• Take significant ownership of microarchitectural decisions and hardware implementation strategy.
• Influence the development of first-generation silicon while shaping future chip architectures.
• Work directly with a highly technical engineering team across architecture, RTL, verification, and physical design.
• Remain deeply involved in technical problem-solving and implementation rather than operating solely at a high-level architectural capacity.
• Contribute to an ambitious AI hardware platform focused on improving the efficiency and performance of LLM inference.

Interview Process

The hiring process typically includes two to three conversations focused on previous technical projects, chip architecture experience, and engineering problem-solving.

References may be requested.

Further details about the company, technology, and roadmap will be shared under NDA as candidates progress through the interview process.