AI Hardware Architect - Energy-Efficient ASIC for LLMs

Normal Computing Corp.; Mountain View (CA); On-site; USD 180,000 - 300,000; Full time

Job summary

Normal Computing in Mountain View, CA, seeks a Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform, delivering energy-efficient inference for LLMs and diffusion models. You will lead co-design across hardware and software, translating research into RTL-ready specifications and validated pre-silicon plans.

You will collaborate with compiler, RTL, and analog teams, building performance models and ensuring throughput-per-watt gains on

Qualifications

• A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience.
• Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic.
• Fluency moving between algorithm-level analysis and hardware specification.
• Experience with simulation-driven architecture.
• Familiarity with quantization and reduced-precision approaches for inference.

Responsibilities

• Define silicon and system microarchitecture for AI accelerator compute blocks.
• Translate workload analysis into hardware specifications and microarchitecture documents.
• Defend PPA tradeoffs across the full stack from algorithm to physical design.
• Partner on ISA co-design with the compiler team.
• Direct block-level pre-silicon validation and de-risk decisions before tapeout.
• Stay current with AI accelerator research and articulate differences from existing solutions.

Skills

Compute Architecture

Workload-to-Hardware Translation

Full-Stack PPA Tradeoffs

ISA Co-Design

Prototyping Strategy

Research Fluency

Python/C++ performance modeling

SystemVerilog

Education

Electrical Engineering or Computer Engineering degree

PhD welcome but not required

Tools

SystemVerilog

Python

C++

Job description

Normal Computing in Mountain View, CA, seeks a Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform, delivering energy-efficient inference for LLMs and diffusion models. You will lead co-design across hardware and software, translating research into RTL-ready specifications and validated pre-silicon plans.

You will collaborate with compiler, RTL, and analog teams, building performance models and ensuring throughput-per-watt gains on