Wafer Architect: AI Chip System Lead (Multi‑Die)

Conductor; Austin, Boston, San Francisco (TX, MA, CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Conductor seeks an architect to own the logical architecture for the A-0 and A-1 wafer products. You will collaborate with the XPU/Compute chip architect and memory architect to synthesize the final wafer-level architecture.

The ideal candidate has deep hands-on experience in AI chip design (GPUs, TPUs, XPUs, ASICs) and strong knowledge of memory subsystems in multi-die configurations, with an emphasis on LLM inference workloads from software to hardware implications.

Qualifications

• Deep understanding of AI chip design processes (GPUs, TPUs, XPUs, ASICs).
• Knowledge of memory subsystems in multi-die systems.
• Understanding of software aspects of LLM inference and its hardware implications.

Responsibilities

• Own the logical architecture for A-0 and A-1 wafer products.
• Collaborate with XPU/Compute chip architect and memory architect to synthesize wafer-level architecture.
• Spearhead architectural partitioning and workload distribution across dies and chip packages.

Skills

AI chip architecture

Multi-die design

LLM inference workloads

Job description

Conductor seeks an architect to own the logical architecture for the A-0 and A-1 wafer products. You will collaborate with the XPU/Compute chip architect and memory architect to synthesize the final wafer-level architecture.

The ideal candidate has deep hands-on experience in AI chip design (GPUs, TPUs, XPUs, ASICs) and strong knowledge of memory subsystems in multi-die configurations, with an emphasis on LLM inference workloads from software to hardware implications.