Senior Physical Design Engineer – First-Gen AI Chip Tapeout

Acceler8 Talent; Palo Alto (CA); On-site; USD 180,000 - 270,000; Full time

Job summary

Acceler8 Talent seeks an experienced Physical Design Engineer to help develop a next-generation AI accelerator chip for LLM inference in an early-stage startup environment.

The role spans ASIC physical implementation, floorplanning, timing closure, power optimization, and tapeout readiness, working closely with RTL, architecture, and implementation teams to meet constraints and performance targets.

Qualifications

• Hands-on experience in digital ASIC physical design and backend implementation.
• Ownership of physical implementation on complex ASIC/SoC designs.
• Strong floorplanning, placement, timing constraints, and physical design optimization.
• Ability to analyze power, performance, and area trade-offs.
• Proven ability to investigate and resolve challenging design closure issues.
• Understanding RTL and microarchitecture impact on backend feasibility.
• Experience collaborating with RTL, architecture, and physical implementation teams.
• Senior-level technical judgment with hands-on involvement in design and debugging.

Responsibilities

• Contribute to floorplanning and physical implementation of complex digital ASIC designs, translating architectural requirements into practical placement and connectivity decisions.
• Analyze and optimize power, performance, and area (PPA) trade-offs throughout the implementation process.
• Identify physical design constraints that require upstream RTL or architectural modifications.
• Investigate and resolve complex physical implementation issues involving floorplanning, timing, power, and design closure.
• Collaborate with RTL and microarchitecture engineers to ensure front-end design decisions align with physical implementation requirements.
• Work with internal engineering teams and external implementation partners to maintain consistent design assumptions and technical handoffs.
• Support physical verification, implementation signoff, and tapeout readiness.
• Track outstanding implementation issues, identify technical risks, and drive engineering solutions through closure.

Skills

ASIC physical design

Floorplanning

Timing closure

Power optimization

Debugging

RTL collaboration

Backend implementation

Tapeout readiness

Tools

STA tools

Synthesis-to-layout

EDA tools

Power integrity analysis

Job description

Acceler8 Talent seeks an experienced Physical Design Engineer to help develop a next-generation AI accelerator chip for LLM inference in an early-stage startup environment.

The role spans ASIC physical implementation, floorplanning, timing closure, power optimization, and tapeout readiness, working closely with RTL, architecture, and implementation teams to meet constraints and performance targets.