Semiconductor Packaging Integration Research Manager

Jobtailor; Arizona; On-site; USD 170,000 - 250,000; Full time

Job summary

Jobtailor seeks a leader to drive advanced packaging integration research in the United States. You will guide a multidisciplinary team to translate system requirements into robust package solutions, focusing on heterogeneous integration, chiplets, 2.5D/3DIC, and wafer-level packaging.

You will define strategy, roadmaps, milestones, and decision criteria aligned to product scaling. The role requires collaboration with silicon design, substrates, assembly, reliability, and manufacturing teams,

Qualifications

• Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
• Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations.
• Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
• Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.
• Master’s degree in electrical engineering, Mechanical Engineering, Materials Science, Chemical Engineering, Applied Physics, Microelectronics, Semiconductor Manufacturing, or related engineering/science discipline; Ph.D. preferred.
• Minimum of 7 years of experience in semiconductor technology roles.
• Preferred experience in semiconductor packaging integration, heterogeneous integration, chiplet architectures, 2.5D/3DIC, hybrid bonding, interposer technology, or package-system co-optimization.

Responsibilities

• Lead advanced packaging integration research programs and multidisciplinary teams.
• Define integration strategy, roadmaps, milestones, and decision criteria aligned to product scaling needs.
• Partner with silicon design, substrates, assembly, reliability, thermal, and manufacturing teams to close cross-domain gaps.
• Translate system requirements into package integration solutions balancing performance, power, area, latency, bandwidth, thermal behavior, reliability, and manufacturability.
• Drive feasibility studies, architecture trade-offs, process module evaluation, design rule development, prototyping, and experimental validation.
• Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews.
• Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer.
• Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths.
• Communicate progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders.
• Collaborate with universities, consortia, suppliers, equipment vendors, research labs, OSATs, foundry partners, design teams, and customer technology teams.

Skills

Advanced Packaging Integration

Chiplet Architectures

Heterogeneous Integration

Technology Readiness Assessment

Cross-Functional Collaboration

Education

Master's Degree in Electrical Engineering

Ph.D. Preferred

Tools

Thermal-Mechanical Modeling

Electromigration Analysis

High-Speed I/O

Power Integrity Tools

Data Center Technologies

Job description

• Lead advanced packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnect technologies
• Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system-level scaling requirements
• Manage a multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, designers, and technical program leads
• Translate system requirements into package integration solutions balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability
• Partner with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal integrity, power delivery, failure analysis, and manufacturing teams to close cross-domain integration gaps
• Drive feasibility studies, architecture trade-off analysis, process module evaluation, design rule development, prototyping, design-of-experiments, and experimental validation
• Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews
• Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer
• Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths
• Communicate technical progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders
• Collaborate with universities, consortia, suppliers, equipment vendors, research labs, OSATs, foundry partners, design teams, and customer technology teams

Requirements

• Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations
• Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations
• Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs
• Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences
• Master’s degree in electrical engineering, Mechanical Engineering, Materials Science, Chemical Engineering, Applied Physics, Microelectronics, Semiconductor Manufacturing, or a related engineering or science discipline
• Minimum of 7 years of experience in semiconductor technology roles
• Must consent to and pass an extended Background Investigation, including extended education, SEC sanctions, and additional criminal and civil checks, subject to country law
• Ph.D. preferred
• Preferred experience in semiconductor packaging integration, heterogeneous integration, chiplet architectures, 2.5D/3DIC, hybrid bonding, interposer technology, fan-out, wafer-level packaging, substrate technology, or package-system co-optimization
• Preferred experience with research-to-development transfer, technology readiness frameworks, pathfinding, prototype builds, process integration learning, and early manufacturing feasibility assessment
• Preferred knowledge of thermal-mechanical modeling, warpage, stress, CTE mismatch, electromigration, reliability physics, high-speed I/O, power integrity, signal integrity, die-to-die interfaces, and package-level co-design
• Preferred record of patents, publications, conference presentations, industry consortia participation, university research collaboration, or external ecosystem leadership
• Preferred experience leading multi-organization collaborations with suppliers, equipment vendors, universities, research labs, OSATs, foundry partners, design teams, or customer technology teams
• Preferred familiarity with AI, HPC, data center, automotive, mobile, networking, edge computing, advanced memory, or custom silicon packaging requirements

Core Competencies

Demonstrates expertise in leading advanced packaging integration research programs, focusing on heterogeneous integration, chiplet architectures, and wafer-level packaging. Proficient in translating complex system requirements into actionable integration solutions while managing multidisciplinary teams and collaborating with various stakeholders.

Highest-signal resume keywords

• Advanced Packaging Integration
• Chiplet Architectures
• Heterogeneous Integration
• Technology Readiness Assessment
• Cross-Functional Collaboration

Hard Skills

• Package-System Integration
• Wafer-Level Processes
• Thermal-Mechanical Behavior
• Signal Integrity
• Reliability Physics
• Process Integration Learning
• Prototype Builds
• Experimental Validation
• Design Rule Development
• Failure Analysis

Soft Skills

• Strong Communication Skills
• Leadership
• Team Management
• Strategic Recommendations
• Problem Solving

Certifications & Qualifications

• Master's Degree in Electrical Engineering
• Ph.D. Preferred

Industry Keywords

• Semiconductor Technology
• Advanced Memory
• Custom Silicon Packaging
• AI
• HPC
• Mobile
• Networking
• Edge Computing
• OSATs
• Foundry Partners

Tools & Technologies

• Thermal-Mechanical Modeling
• Electromigration Analysis
• High-Speed I/O
• Power Integrity Tools
• Data Center Technologies