Power Architect, SoC DVFS & Thermal Control

Velaura; Santa Clara (CA); On-site; USD 200,000 - 350,000; Full time

Job summary

Velaura in Santa Clara, CA is seeking an RTL Engineer focused on power management for the next-generation Physical AI SoC. You will own power management at all levels, collaborating with architects, performance modelers, software and firmware teams to translate architectural concepts into silicon.

You will design on-chip power management hardware, clock and reset architectures, and DVFS-based power state control, ensuring robust thermal and power behavior across the die and packages.

Qualifications

• Strong grasp of average power, peak current, thermal behavior and voltage droop and how these relate.
• Experience designing power management hardware such as digital power meters, throttlers, or thermal and current control loops.
• Understanding of di/dt, IR drop and power delivery network behavior and their impact on timing margin.
• Experience with clock and reset architecture including clock gating, PLL management and reset sequencing.
• Working knowledge of Verilog or SystemVerilog and modern RTL design methodology.
• Experience with power estimation and analysis flows from RTL through gate level.
• Strong debugging and problem solving skills across hardware and software boundaries.
• BS or higher in Electrical Engineering, Computer Engineering or a related field.

Responsibilities

• Design the on chip power management hardware for the Velaura SoC including digital power meters, activity monitors and throttlers.
• Design hardware and software control loops around temperature sensors that hold the die under a defined thermal limit.
• Design controls that keep the design under defined activity and average power limits as well as instantaneous di/dt limits.
• Work with architects, physical design and package teams on voltage droop behavior, power delivery and adaptive clocking response.
• Own clock and reset architecture including clock gating, PLL programming and management, and reset sequencing across power domains.
• Define and implement power state management including DVFS, power domains, retention and low power flows.
• Correlate power estimates across RTL, emulation and silicon, and build the telemetry that makes power and thermal behavior visible in the field.
• Work with firmware and software teams on the interfaces, policies and telemetry that drive power and thermal management.

Skills

Power management hardware design

RTL design experience

Verilog/SystemVerilog

Power estimation & analysis

Debugging across HW/SW

DVFS

Education

BS in Electrical Engineering or Computer Engineering

Tools

PowerArtist

PrimePower

Joules

Job description

Velaura in Santa Clara, CA is seeking an RTL Engineer focused on power management for the next-generation Physical AI SoC. You will own power management at all levels, collaborating with architects, performance modelers, software and firmware teams to translate architectural concepts into silicon.

You will design on-chip power management hardware, clock and reset architectures, and DVFS-based power state control, ensuring robust thermal and power behavior across the die and packages.