RTL Integration Engineer

Sintegra Inc.; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

We are looking for an experienced RTL Integration Engineer to join our ASIC/SoC design team. The successful candidate will be responsible for integrating RTL blocks, subsystems, and IP into top-level designs, ensuring functional correctness, performance optimization, and seamless handoff to verification and physical design teams.

Key responsibilities include owning and executing RTL integration, developing and maintaining top-level RTL and interconnect and clock/reset integration logic, ensuring

Qualifications

• Experience integrating RTL blocks, subsystems, and IP into top-level designs.
• Ability to meet functional, power, performance, and area targets.
• Experience collaborating with verification and physical design teams.

Responsibilities

• Own and execute RTL integration of IPs and subsystems into the SoC top-level.
• Develop and maintain top-level RTL, interconnect, and clock/reset integration logic.
• Ensure design meets functional, power, performance, and area (PPA) targets.
• Collaborate with front-end and back-end teams to close on timing, lint, CDC, RDC, and synthesis requirements.
• Drive integration best practices including hierarchy definition, naming conventions, and signal integrity.
• Debug and resolve integration-related functional and structural issues.
• Generate and maintain design collaterals (netlists, constraints, scripts, documentation).
• Work with verification teams to enable testbenches, simulations, and regression infrastructure for SoC-level validation.
• Support emulation/FPGA bring-up and silicon validation teams for integration-related debug.

Skills

RTL integration

SoC design

Timing closure

Debugging

Tools

Synthesis

Emulation

FPGA bring-up

Job description

We are looking for an experienced RTL Integration Engineer to join our ASIC/SoC design team. The successful candidate will be responsible for integrating RTL blocks, subsystems, and IP into top-level designs, ensuring functional correctness, performance optimization, and seamless handoff to verification and physical design teams.

Key Responsibilities

• Own and execute RTL integration of IPs and subsystems into the SoC top-level.
• Develop and maintain top-level RTL, interconnect, and clock/reset integration logic.
• Ensure design meets functional, power, performance, and area (PPA) targets.
• Collaborate with front-end and back-end teams to close on timing, lint, CDC, RDC, and synthesis requirements.
• Drive integration best practices including hierarchy definition, naming conventions, and signal integrity.
• Debug and resolve integration-related functional and structural issues.
• Generate and maintain design collaterals (netlists, constraints, scripts, documentation).
• Work with verification teams to enable testbenches, simulations, and regression infrastructure for SoC-level validation.
• Support emulation/FPGA bring-up and silicon validation teams for integration-related debug.