RTL Frontend Design Engineer: Synthesis & Timing

Apple, Inc.; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking an RTL Design Engineer to convert RTL designs into optimized netlists, using industry-standard synthesis tools.

You will work on balancing power, performance and area while refining existing synthesis methods. You will understand Verilog and SystemVerilog, guide RTL solutions, perform CDC/RDC checks, Lint, and STA, analyze waveforms, and collaborate with internal R&D teams.

Qualifications

• Master's degree or foreign equivalent in Electrical and Computer Engineering or related field with 1 year of experience.
• Understanding RTL and updates for PPA.
• Creating unit testbenches to verify RTL updates.
• Working with simulation waveforms to understand design intent.
• Performing Static Timing Analysis (STA) and achieving timing closure.
• Performing Lint checks to ensure RTL quality.

Responsibilities

• Convert RTL designs into netlists using industry-standard RTL synthesis tools.
• Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies.
• Understand RTL code written in Verilog and SystemVerilog, correlating it to gate-level circuits.
• Guide the development of optimal RTL solutions.
• Perform Clock and Reset Domain Crossing (CDC/RDC) checks for robustness.
• Perform logical equivalence checks to verify generated netlists.
• Support ECO generation activities and conduct STA to identify critical paths.
• Analyze RTL simulation waveforms to understand design intent and signal activity.
• Lint checks to ensure RTL quality and collaborate with internal R&D teams.

Skills

RTL design

RTL updates for PPA

Verilog

SystemVerilog

Testbench

Simulation waveforms

Static Timing Analysis

Lint checks

Education

Master's degree in Electrical and Computer Engineering or related field

Job description

Apple Inc. in Austin, Texas is seeking an RTL Design Engineer to convert RTL designs into optimized netlists, using industry-standard synthesis tools.

You will work on balancing power, performance and area while refining existing synthesis methods. You will understand Verilog and SystemVerilog, guide RTL solutions, perform CDC/RDC checks, Lint, and STA, analyze waveforms, and collaborate with internal R&D teams.