Front End Design Engineer

Apple, Inc.; Austin (TX); Sur place; USD 110 000 - 170 000; Plein temps

Résumé du poste

Apple Inc. in Austin, Texas is seeking an RTL Design Engineer to convert RTL designs into optimized netlists, using industry-standard synthesis tools.

You will work on balancing power, performance and area while refining existing synthesis methods. You will understand Verilog and SystemVerilog, guide RTL solutions, perform CDC/RDC checks, Lint, and STA, analyze waveforms, and collaborate with internal R&D teams.

Qualifications

• Master's degree or foreign equivalent in Electrical and Computer Engineering or related field with 1 year of experience.
• Understanding RTL and updates for PPA.
• Creating unit testbenches to verify RTL updates.
• Working with simulation waveforms to understand design intent.
• Performing Static Timing Analysis (STA) and achieving timing closure.
• Performing Lint checks to ensure RTL quality.

Responsabilités

• Convert RTL designs into netlists using industry-standard RTL synthesis tools.
• Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies.
• Understand RTL code written in Verilog and SystemVerilog, correlating it to gate-level circuits.
• Guide the development of optimal RTL solutions.
• Perform Clock and Reset Domain Crossing (CDC/RDC) checks for robustness.
• Perform logical equivalence checks to verify generated netlists.
• Support ECO generation activities and conduct STA to identify critical paths.
• Analyze RTL simulation waveforms to understand design intent and signal activity.
• Lint checks to ensure RTL quality and collaborate with internal R&D teams.

Connaissances

RTL design

RTL updates for PPA

Verilog

SystemVerilog

Testbench

Simulation waveforms

Static Timing Analysis

Lint checks

Formation

Master's degree in Electrical and Computer Engineering or related field

Description du poste

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Convert RTL designs into netlists using industry-standard RTL synthesis tools. Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies. Understand RTL code written in Verilog and SystemVerilog languages, correlate it to gate-level circuits, and guide the development of optimal RTL solutions. Perform Clock and Reset Domain Crossing (CDC,RDC) checks to ensure the design's robustness against metastability-related problems and lint checks. Perform logical equivalence checks to ensure correctness of the generated netlist and support ECO generation activities. Perform static timing analysis (STA) to identify critical paths in the design, then propose solutions spanning both physical implementation and microarchitectural optimizations. Analyze RTL simulation waveforms using industry standard simulator tools to understand the design's intent and common signal activity pattern. Lint checks to ensure the overall quality of RTL code. Collaborate effectively with internal R&D teams. 40 hours/week.

Minimum Qualifications

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field and 1 year of experience in the job offered or related occupation.
• Experience and/or education must include:
• Understanding RTL and make RTL updates for PPA
• Creating unit testbench to verify RTL updates
• Working with simulation waveform to understand design intent
• Performing Static Timing Analysis (STA) and achieving timing closure
• Performing Lint checks to ensure RTL quality

Preferred Qualifications

• N/A

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