SOC Micro-Architect and RTL Designer

Acceler8 Talent; Mountain View (CA); Hybrid; USD 180,000 - 220,000; Full time

Job summary

Acceler8 Talent is seeking a SoC Micro-Architect & RTL Designer for a hybrid role in Mountain View, CA, with on-site Tue–Thu. We’re a well-funded AI semiconductor startup building a processor architecture for frontier-scale language models, co-designing silicon and software around throughput, latency, memory, and interconnect demands.

You’ll translate architectural requirements into production‑quality microarchitecture and RTL, own blocks from spec to sign‑off, and optimize compute, memory, and

Qualifications

• 5+ years of SoC/ASIC microarchitecture and RTL design experience.
• Strong SystemVerilog skills; proficient with Python or C/C++.
• Experience delivering designs toward production silicon.
• Hands-on with synthesis, lint, CDC, and equivalence checking.
• Experience with high-performance compute, memory, or connectivity designs.
• Understanding RTL decisions impact on timing, power, area.

Responsibilities

• Translate architectural requirements into RTL and microarchitecture.
• Own subsystems from spec to sign-off.
• Develop compute, memory‑management, or high‑speed‑connectivity functionality.
• Optimize performance, power, area, and timing.
• Collaborate across verification, DFT, physical design, architecture, and software.
• Support silicon bring‑up and debug.

Skills

SoC microarchitecture

RTL design

SystemVerilog

Python

C/C++

Synthesis

Lint

CDC

Equivalence checking

Compute design

Memory design

Interconnect design

Tools

Python

SystemVerilog

Job description

SoC Micro-Architect & RTL Designer

Hybrid – Mountain View, CA | Tuesday–Thursday on-site

$200k+ base + RSUs

I’m working with a well-funded AI semiconductor startup building a new processor architecture specifically for frontier-scale language models.

Rather than adapting a general-purpose GPU, the team is co-designing the silicon and software around the throughput, latency, memory, and interconnect demands of large-model training and inference.

The company is moving its first-generation platform toward tape-out and product delivery, giving engineers the opportunity to influence important architectural and implementation decisions before conventions become fixed.

You’ll work on problems such as:

• Translating architectural requirements into production-quality microarchitecture and RTL
• Owning blocks or subsystems from specification through sign-off
• Developing compute, memory‑management, or high‑speed‑connectivity functionality
• Optimizing performance, power, area, and timing
• Working across verification, DFT, physical design, architecture, and software
• Supporting silicon bring‑up and debug

Looking for engineers who have:

• 5+ years of SoC or ASIC microarchitecture and RTL‑design experience
• Strong SystemVerilog skills, plus experience with Python or C/C++
• Experience taking complex designs toward production silicon
• Hands‑on knowledge of synthesis, lint, CDC, and equivalence checking
• Experience delivering high‑performance compute, memory, or connectivity designs
• A clear understanding of how RTL decisions affect timing, power, area, and physical implementation.

Nice to have:

• PCIe, HBM, DMA, or die‑to‑die subsystem experience
• CPU, GPU, or machine‑learning accelerator experience
• Emulation, silicon bring‑up, or post‑silicon debug experience
• Ownership of a complete subsystem through tape‑out.

The strongest candidates will be able to explain what they personally architected, implemented, closed, and delivered on previous silicon programmes.

Candidates must be authorized to work in the United States and able to work from the Mountain View office Tuesday through Thursday.