RTL Design / Microarchitecture Engineer

Bolt Graphics, Inc.; Sunnyvale (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

Medical, Dental, & Vision - 100% covered premiums

Equity - Stock Options

401(k) match

Job summary

A semiconductor startup in Sunnyvale, CA is looking for an experienced RTL Design / Microarchitecture Engineer. This role involves defining and implementing key microarchitectural components, working closely with multiple teams for high-performance, power-efficient designs. Required qualifications include a Bachelor’s/Master’s in Electrical Engineering and 5–10 years of RTL design experience. The position offers a competitive salary range of $160,000–$220,000 per year along with comprehensive benefits including medical coverage and stock options.

Qualifications

• 5–10 years of experience in RTL design and microarchitecture.
• Strong expertise in performance optimization and pipelining techniques.
• Experience in ASIC/SoC development environments.

Responsibilities

• Define and develop microarchitecture specifications.
• Design and implement RTL (SystemVerilog/Verilog) for complex digital blocks.
• Drive performance, power, and area optimizations.

Skills

Performance optimization techniques

Pipelining techniques

Simulation and debugging tools

Digital design fundamentals

ASIC/SoC development

Education

Bachelor’s/Master’s degree in Electrical Engineering or related field

Tools

Synopsys VCS

Cadence Xcelium

Synopsys Design Compiler

Job description

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

• Be Fearless: Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
• Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role

As an RTL Design / Microarchitecture Engineer, you will define and implement key microarchitectural components of our SoC/IP. You will work closely with architecture, verification, and physical design teams to deliver high-performance, scalable, and power-efficient designs.

What you'll do

• Define and develop microarchitecture specifications from high-level architecture requirements.
• Design and implement RTL (SystemVerilog/Verilog) for complex digital blocks.
• Drive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level.
• Collaborate with verification teams to ensure high coverage and design correctness.
• Support integration of IPs into SoC-level environments.
• Work with physical design teams for timing closure, synthesis constraints, and floorplan-aware design.
• Debug and resolve issues during simulation, GLS, and silicon bring-up.
• Participate in design reviews, architecture discussions, and cross-functional planning.
• Contribute to design documentation and methodology improvements.

Required Qualifications

• Bachelor’s/Master’s degree in Electrical Engineering or related field.
• 5–10 years of experience in RTL design and microarchitecture.
• Strong expertise in:
  • Performance optimization and pipelining techniques.
  • Experience with simulation and debugging tools such as:
  • Synopsys VCS/Cadence Xcelium.
  • Familiarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler).
  • Strong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces).
  • Experience working in ASIC/SoC development environments.

Preferred Qualifications

• Experience in one or more domains:
  • CPU, GPU, AI/ML accelerators, networking, or high-speed data processing.
• Knowledge of memory subsystem design (SRAM, cache hierarchies, coherency).
• Familiarity with low-power design techniques (clock gating, power domains).
• Exposure to formal verification or linting tools.
• Experience with GLS, SDF annotation, and silicon debug.
• Understanding of hardware-software interaction (firmware, drivers).

Compensation Range

$160,000–$220,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.

Benefits

• Medical, Dental, & Vision - 100% covered premiums.
• Equity - Stock Options.
• 401(k) match.

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.