SOC Micro-Architect & RTL Designer

Platform Recruitment; San Francisco (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

Generous PTO

Medical/dental/vision

401(k) match

Parental leave

Professional development budget

Commute/home-office support

Job summary

Platform Recruitment is seeking silicon engineers to own end-to-end design for next-gen ASICs/SoCs. You’ll influence architecture, micro-architecture and RTL sign-off while coordinating with verification, DFT and physical design to achieve top-tier PPA.

Hybrid role with on-site days in the Bay Area and remote considered for the right candidate. Ideal background includes 5+ years in SystemVerilog, Python and C/C++, with hands-on experience in high-performance compute, memory management or

Qualifications

• 5+ years of SystemVerilog, Python and C/C++ in chip design and flows.
• Experience driving ASIC/SoC design from architecture to production silicon.
• Hands-on with synthesis, equivalence checking, lint and clock-domain-crossing.

Responsibilities

• Contribute to architecture-to-design methodology across blocks and full-chip design.
• Own subsystem or chip-level deliverables from micro-architecture through RTL sign-off.
• Plan reviews for micro-architecture, specs, progress, and timing/area closure.
• Collaborate with verification, DFT and physical design teams to optimize PPA.

Skills

SystemVerilog

Python

C/C++

Chip design flows

Tools

Synthesis

Equivalence checking

Lint

Timing closure

DFT

Physical design

Job description

Location: Bay Area, CA (hybrid, on-site a few days/week) — remote considered for the right candidate

Type: Full-time

Department: Hardware / Silicon

About the Role

A high-performance silicon team is building next-generation ASICs/SoCs for large-scale AI and ML workloads. We're hiring silicon micro-architects and design engineers to own performant, functionally accurate silicon across compute, memory management, and high-speed connectivity, from micro-architecture through sign-off.

What You'll Do

• Contribute to a scalable architecture-to-design methodology spanning blocks, subsystems, and full-chip design
• Own subsystem and/or chip-level design deliverables end to end, from micro-architecture through sign-off-ready RTL
• Plan and drive intermediate and sign-off reviews covering micro-architecture, design specs, execution progress, and area/timing closure toward design freeze and tapeout
• Partner closely with verification, DFT, and physical design co-owners to deliver best-in-class PPA (performance, power, area)

What We're Looking For

• Concept-to-silicon experience driving subsystem and/or top-level ASIC/SoC design from architecture spec to production silicon
• 5+ years with SystemVerilog, Python, and C/C++ (and related scripting/programming for chip design flows)
• Production-proven micro-architecture and design experience in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, and/or memory management
• Hands-on with design synthesis, equivalence checking, lint, and clock-domain-crossing flows to reach high-quality sign-off
• Solid grasp of DFT and physical design concepts, working alongside specialists to close timing, power, area, and test coverage
• Experience collaborating with verification teams toward performance and coverage closure

Nice to Have

• Familiarity with verification, emulation platforms, and methodologies
• Silicon debug and bring-up experience
• Hands-on silicon/firmware experience with PCIe, HBM, DMA, or die-to-die subsystems

Compensation

Competitive base scaled by experience level, from roughly $160K to $600K, plus meaningful equity. Strong benefits package including generous PTO, subsidized medical/dental/vision, 401(k) match, parental leave, professional development budget, and commute/home-office support.

Please Note

This role requires access to information subject to U.S. export control regulations. Candidates must be able to perform the role in compliance with U.S. export control laws.