RTL Design Lead for SoC Front-End & IP

Advanced Micro Devices, Inc.; San Jose, Northern (CA, KY); Hybrid; USD 180,000 - 270,000; Full time

Job summary

AMD seeks an RTL Design Manager for the AECG IP & SOC group in San Jose, CA. You will lead front-end RTL engineering, collaborate across architecture, IP design, and physical design teams, and drive first-pass silicon success.

The role emphasizes strong communication, problem solving, and ability to balance timing, area, and power while guiding verification and automation efforts across a small team.

Qualifications

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

Responsibilities

• Lead a small, high-performance engineering team.
• Own the design and implementation of blocks to meet functional, timing, area and power requirements.
• Guide and review verification for these blocks.
• Design and implement logic functions that enable efficient test and debug.
• Implement automation to increase design team efficiency.

Skills

RTL engineering

Communication

Analytical thinking

Arm architecture

APB/AXI/CHI protocols

Design reuse

SoC integration

Automation scripting

Timing constraints

LINT/CDC checks

UPF power domains

Self-motivated

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

PERL

Python

Tcl

Job description

AMD seeks an RTL Design Manager for the AECG IP & SOC group in San Jose, CA. You will lead front-end RTL engineering, collaborate across architecture, IP design, and physical design teams, and drive first-pass silicon success.

The role emphasizes strong communication, problem solving, and ability to balance timing, area, and power while guiding verification and automation efforts across a small team.