RTL Design Engineer - Timing & Synthesis (Onsite Bay Area)

Inabia Software & Consulting Inc.; San Francisco (CA); On-site; USD 130,000 - 180,000; Full time

Job summary

Inabia Software & Consulting Inc. seeks a Design Engineer with extensive RTL synthesis and timing analysis experience for Bay Area onsite work.

You will handle RTL synthesis, constraint writing, and STA while developing scripts for synthesis and timing closure, and will debug timing issues to deliver clean netlists. Ideal candidates have 8–12 years of RTL Synthesis hands-on experience, with exposure to major EDA tools and multi-node design flows at advanced nodes like 16nm and 7nm.

Qualifications

• 8–12 years of hands-on RTL Synthesis experience.
• Experience with EDA tools such as Design Compiler, PrimeTime, Tempus, Genus.
• Experience working on multi-node designs (e.g., 16nm, 7nm).

Responsibilities

• RTL Synthesis, Constraint writing, validation, and Static Timing Analysis.
• Write/modify scripts for RTL synthesis, SDC creation, and STA.
• Debug synthesis issues and STA to generate clean netlists.

Skills

RTL Synthesis

Constraint writing

Static timing Analysis

Debug STA

Tools

Design compiler

PrimeTime

Tempus

Genus

Job description

Inabia Software & Consulting Inc. seeks a Design Engineer with extensive RTL synthesis and timing analysis experience for Bay Area onsite work.

You will handle RTL synthesis, constraint writing, and STA while developing scripts for synthesis and timing closure, and will debug timing issues to deliver clean netlists. Ideal candidates have 8–12 years of RTL Synthesis hands-on experience, with exposure to major EDA tools and multi-node design flows at advanced nodes like 16nm and 7nm.