Bay Area RTL2PD Design Engineer (ASIC) – Onsite

Inabia-Software-; San Francisco (CA); On-site; USD 103,000 - 110,000; Full time

Job summary

Inabia-Software- in the Bay Area seeks an experienced RTL2PD Design Engineer to drive RTL synthesis, constraint writing, validation, and STA for ASIC flows, with scripting for RTL synthesis and STA. This onsite role requires deep hands-on expertise across 16nm/7nm nodes and collaboration with design teams.

Proficiency with Design Compiler, PrimeTime, Tempus, and Genus is essential. You will generate clean netlists and debug synthesis issues to meet timing objectives.

Qualifications

• 8–12 years of hands-on RTL Synthesis experience.
• Experience with 16nm and 7nm nodes is preferred.
• Visa-friendly; C2C engagements allowed.

Responsibilities

• RTL Synthesis, Constraint writing, validation, and STA.
• Write/modify scripts for RTL synthesis, SDC creation, and STA.
• Debug synthesis issues and STA to generate clean netlists.
• Perform RTL2PD tasks onsite in the Bay Area.

Skills

RTL Synthesis

Constraint Writing

Validation

STA

Scripting

Tools

Design Compiler

PrimeTime

Tempus

Genus

Job description

Inabia-Software- in the Bay Area seeks an experienced RTL2PD Design Engineer to drive RTL synthesis, constraint writing, validation, and STA for ASIC flows, with scripting for RTL synthesis and STA. This onsite role requires deep hands-on expertise across 16nm/7nm nodes and collaboration with design teams.

Proficiency with Design Compiler, PrimeTime, Tempus, and Genus is essential. You will generate clean netlists and debug synthesis issues to meet timing objectives.