RTL Design Engineer

Inabia-Software-; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Arrow Electronics is seeking a Design Engineer for the Bay Area (onsite) to drive RTL2PD activities. The candidate will contribute to RTL synthesis, constraint writing, validation, and Static Timing Analysis within an RTL2PD to Physical Design flow.

The role requires 8–12 years of hands-on RTL Synthesis experience, familiarity with Design Compiler, PrimeTime, Tempus, Genus, and experience across 16nm and 7nm process nodes. Scripting for RTL, SDC, and STA is essential.

Qualifications

• 8–12 years of hands‑on RTL Synthesis experience.
• Experience with 16nm, 7nm process nodes.
• Proficient with Design Compiler, PrimeTime, Tempus, Genus.
• Strong timing closure and STA debugging skills.
• Scripting for RTL synthesis and SDC creation.

Responsibilities

• RTL Synthesis, Constraint writing, validation, Static timing Analysis
• Writing scripts/modifying scripts for RTL synthesis, SDC creation, STA
• Debug synthesis issues and STA
• Generate clean netlist.

Skills

RTL Synthesis

Constraint writing

Validation

Static timing Analysis

Design Compiler

PrimeTime

Tempus

Genus

Scripting for RTL

Multi-node design

Tools

Design Compiler

PrimeTime

Tempus

Genus

Job description

• Job Title : Design Engineer
• Client: Arrow Electronics
• Work Location:Bay Area ,CA, onsite
• Visa: All visa, except H1B transfer
• C2C engagements are allowed.

Need Design Engineer with very strong experience Timing ConstraintsWriting. (this must reflect in resume)

RTL to Physical Design (RTL2PD) stage experience

RTL2PD Design Engineer(ASIC)

MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis

What candidate will Be Doing:

• RTL Synthesis, Constraint writing, validation, Static timing Analysis
• Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA
• Debug synthesis issues and STA
• Generate clean netlist.

What we are looking for:

• Experience: 8–12 years of hands‑on RTL Synthesis
• EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
• Multi-Node Design: Experience working with 16nm, 7nm... etc nodes.