RTL Design Engineer, Silicon (ASIC/IP)

Google Inc.; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Mountain View, CA, is seeking an RTL Design Engineer in Silicon to contribute to custom silicon powering Google devices. You will define microarchitecture, integrate IP, and perform RTL coding and verification.

Requirements include a Bachelor's in EE/CE/CS or related field, 4 years of IP development or integration experience, and proficiency in Verilog or VHDL; scripting in Python or Perl is preferred. Master/PhD plus ASIC/DFT experience preferred.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development with Verilog or VHDL.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Define microarchitecture for a subsystem.
• Integrate internal and/or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

RTL design

Verilog/VHDL

Python/Perl

IP development

ASIC development

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field

Job description

Google Mountain View, CA, is seeking an RTL Design Engineer in Silicon to contribute to custom silicon powering Google devices. You will define microarchitecture, integrate IP, and perform RTL coding and verification.

Requirements include a Bachelor's in EE/CE/CS or related field, 4 years of IP development or integration experience, and proficiency in Verilog or VHDL; scripting in Python or Perl is preferred. Master/PhD plus ASIC/DFT experience preferred.