RTL Design Engineer, TPU

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Benefits offered by this job

15% bonus target

Equity options

Comprehensive benefits

Job summary

Google Inc. in Sunnyvale, CA is seeking an experienced engineer for an ASIC design role focused on management and control subsystem design. The successful candidate will work on SystemVerilog RTL for ASIC products and collaborate with architecture, validation, and hardware teams.

Applicants should have a Bachelor’s degree in Electrical Engineering or a related field and possess significant experience in ASIC design. The position offers a competitive compensation package including a bonus and equity options.

Qualifications

• Bachelor's degree in a relevant field or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience interacting with software and hardware teams.

Responsibilities

• Design RTL Intellectual Property focusing on management and control.
• Develop SystemVerilog RTL for ASIC products.
• Collaborate with teams to evaluate features and their impact.

Skills

Experience with scripting languages

Understanding of digital design fundamentals

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree or PhD in related fields

Tools

SystemVerilog

I2C

SPI

UART

Job description

Google, Sunnyvale, CA, USA

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross‑functional teams.
• Experience with chip management, clocking, reset, and peripherals such as I2C, SPI, UART.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

• Design RTL Intellectual Property (IP) focusing on management and control subsystem.
• Develop SystemVerilog RTL to implement logic for ASIC products according to coding and quality guidelines.
• Collaborate with architecture and power teams to evaluate features and their impact.
• Collaborate with design validation teams to create test plans, verify, and debug RTL.
• Collaborate with physical design teams to ensure design meets physical requirements and timing closure.
• Build a global understanding of accelerator development from concept to production.
• Coordinate and co‑design with software and system hardware counterparts.
• Leverage design and verification expertise to verify complex digital designs, focusing on TPU architecture and its integration within AI/ML‑driven systems.

US compensation: $163,000–$237,000 (USD) + 15% bonus target + equity + benefits.

Benefits

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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