RTL Design Engineer, Silicon

Google Inc.; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google Mountain View, CA, is seeking an RTL Design Engineer in Silicon to contribute to custom silicon powering Google devices. You will define microarchitecture, integrate IP, and perform RTL coding and verification.

Requirements include a Bachelor's in EE/CE/CS or related field, 4 years of IP development or integration experience, and proficiency in Verilog or VHDL; scripting in Python or Perl is preferred. Master/PhD plus ASIC/DFT experience preferred.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development with Verilog or VHDL.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Define microarchitecture for a subsystem.
• Integrate internal and/or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

RTL design

Verilog/VHDL

Python/Perl

IP development

ASIC development

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field

Job description

Google Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development withVerilogor VHDL.
• Experience with a scripting language like Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
• Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Knowledge of high-performance and energy efficient design techniques.
• Knowledge of FPGA and emulation platforms.
• Knowledge of ASIC Verification or DFT.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google .

• Define microarchitecture for a subsystem.
  
• Integrate internal and/or external IP.
  
• Define microarchitecture of a small to medium size IP.
  
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.
  

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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