RTL Design Engineer, Silicon

Google; Mountain View (CA); On-site; USD 150,000 - 223,000; Full time

Job summary

Google in Mountain View, CA is seeking a Mid-level RTL Design Engineer to drive micro-architecture definition and IP integration for an ASIC/subsystem. You will code in RTL languages, perform complex simulations, and contribute to synthesis, timing, and power closure for silicon bring-up.

The role requires 5+ years in RTL design, IP integration, and scripting with Perl or Python, with a bias toward low-power and high-performance designs. Eligible for base salary with bonus and equity.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• 5 years of experience with IP development or integration.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Manage micro-architecture definition for a subsystem/ASIC.
• Perform integration of internal or external IP.
• Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

RTL design

Verilog/SystemVerilog

IP development/integration

Logic synthesis

Scripting (Perl/Python)

Education

Bachelor's degree in ELEC/CompEng/CS

Master's degree or PhD (preferred)

Job description

RTL Design Engineer, Silicon

Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• 5 years of experience with IP Development or Integration.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
• Experience with a scripting language like Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
• Experience with FPGA and emulation platforms.
• Experience with high performance and energy efficient design techniques.
• Experience with ASIC Verification or DFT.
• Knowledge in Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts, or Clocks/Reset.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Manage micro-architecture definition for a subsystem/ASIC.
• Perform integration of internal or external IP.
• Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

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