Silicon RTL Design Engineer — High-Impact IP & ASIC

Google; Mountain View (CA); On-site; USD 150,000 - 223,000; Full time

Job summary

Google in Mountain View, CA is seeking a Mid-level RTL Design Engineer to drive micro-architecture definition and IP integration for an ASIC/subsystem. You will code in RTL languages, perform complex simulations, and contribute to synthesis, timing, and power closure for silicon bring-up.

The role requires 5+ years in RTL design, IP integration, and scripting with Perl or Python, with a bias toward low-power and high-performance designs. Eligible for base salary with bonus and equity.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• 5 years of experience with IP development or integration.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Manage micro-architecture definition for a subsystem/ASIC.
• Perform integration of internal or external IP.
• Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

RTL design

Verilog/SystemVerilog

IP development/integration

Logic synthesis

Scripting (Perl/Python)

Education

Bachelor's degree in ELEC/CompEng/CS

Master's degree or PhD (preferred)

Job description

Google in Mountain View, CA is seeking a Mid-level RTL Design Engineer to drive micro-architecture definition and IP integration for an ASIC/subsystem. You will code in RTL languages, perform complex simulations, and contribute to synthesis, timing, and power closure for silicon bring-up.

The role requires 5+ years in RTL design, IP integration, and scripting with Perl or Python, with a bias toward low-power and high-performance designs. Eligible for base salary with bonus and equity.