RTL Design Engineer: NoC & Networking for AI Accelerators

OpenAI; United States; Remote; USD 180,000 - 280,000; Full time

Job summary

OpenAI’s Hardware organization seeks a highly experienced RTL engineer with deep packet-networking and interconnect expertise to own critical on‑chip communication components for our AI accelerator platform.

You will drive the microarchitecture, RTL implementation, and verification closure, coordinating silicon bring‑up and production readiness while mentoring junior engineers and coordinating with external partners.

Qualifications

• Senior RTL engineer with packet-networking and interconnect expertise.
• Owned production RTL for networking datapaths such as Ethernet switches, NICs, or NoCs.
• Experience driving microarchitecture, SystemVerilog implementation, verification closure, and silicon bring-up.

Responsibilities

• Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components (NoC fabrics, switches, routers, bridges, advisory components).
• Plan and oversee the work of junior engineers and foster productive relationships with external partners.
• Lead designs from requirements through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, and production readiness.

Skills

RTL design

SystemVerilog

Packet-networking

NoC fabrics

Microarchitecture

Verification

Silicon bring-up

Leadership

Job description

OpenAI’s Hardware organization seeks a highly experienced RTL engineer with deep packet-networking and interconnect expertise to own critical on‑chip communication components for our AI accelerator platform.

You will drive the microarchitecture, RTL implementation, and verification closure, coordinating silicon bring‑up and production readiness while mentoring junior engineers and coordinating with external partners.