AI-Driven RTL Design Engineer - Ethernet NICs & SoC

Architect Labs; Palo Alto (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Architect Labs in California seeks a Senior RTL Design Engineer to own AI-driven microarchitectures for high-performance networking subsystems. You will drive Ethernet MAC/PCS blocks, TX/RX pipelines, and datapath integration into production silicon.

You'll collaborate with the architecture, DV, SW, and ML teams, define interface specs, and support FPGA prototyping on Xilinx platforms, ensuring protocol compliance and power-aware design choices.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical or Computer Engineering.
• 5+ years RTL design with at least one advanced-node tapeout in networking or NICs.
• Deep familiarity with IEEE 802.3 Ethernet MAC/PCS, FEC, and multi-lane operation.
• Strong SystemVerilog, linting, and collaboration with DV and SW/ML teams.

Responsibilities

• Own the network datapath RTL end-to-end from MAC to DMA interfaces.
• Design Ethernet MAC engines and PCS layers for multi-speed operation 10G/25G/50G/100G/400G+.
• Architect packet processing datapaths, DMA interfaces, and QoS scheduling.
• Collaborate with the principal architect to refine microarchitectural specs.
• Define and maintain MII/GMII/XGMII/AXI-Stream interfaces and related signaling.

Skills

SystemVerilog

RTL design

Networking

Python

Multi-rate design

PPA/area tradeoffs

Education

Bachelor/Master/PhD in EE/CE

Tools

Xilinx Vivado

Synthesis tools

Job description

Architect Labs in California seeks a Senior RTL Design Engineer to own AI-driven microarchitectures for high-performance networking subsystems. You will drive Ethernet MAC/PCS blocks, TX/RX pipelines, and datapath integration into production silicon.

You'll collaborate with the architecture, DV, SW, and ML teams, define interface specs, and support FPGA prototyping on Xilinx platforms, ensuring protocol compliance and power-aware design choices.