Senior RTL Design Lead – AI Accelerator Data Movement

Acceler8 Talent; San Francisco (CA); Hybrid; USD 180,000 - 300,000; Full time

Job summary

Acceler8 Talent is partnering with a semiconductor startup to shape a new AI inference architecture for data centers. You will own the data movement subsystem from architectural definition to tapeout and silicon optimization.

The role requires deep NoC, memory system expertise and experience in AI accelerators, with strong cross-functional collaboration across RTL, verification, compiler, and performance teams. Senior to principal level, opportunity for significant architectural ownership.

Qualifications

• Deep expertise in NoC architecture, buffering, memory systems, switching fabrics.
• Ownership of data movement or memory hardware across silicon generations.
• Experience designing AI accelerators or high-performance compute architectures.

Responsibilities

• Own architecture and microarchitecture of the data movement subsystem.
• Define and optimize networks, crossbars, switches, buffers, and memories.
• Balance throughput, latency, power, and area with performance models.
• Collaborate with compiler, kernel, performance, RTL, and verification teams.
• Support RTL implementation, timing closure, and silicon bring-up.

Skills

NoC architecture

Memory systems

Data movement

AI accelerators

Performance-per-watt

Silicon bring-up

Education

MS/PhD or equivalent

Tools

RTL verification

ASIC emulation

Tape-out readiness

Job description

Acceler8 Talent is partnering with a semiconductor startup to shape a new AI inference architecture for data centers. You will own the data movement subsystem from architectural definition to tapeout and silicon optimization.

The role requires deep NoC, memory system expertise and experience in AI accelerators, with strong cross-functional collaboration across RTL, verification, compiler, and performance teams. Senior to principal level, opportunity for significant architectural ownership.