RTL Design Engineer — ASIC & IP Integration

Google; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google in Mountain View is hiring for a role that focuses on designing custom silicon for our direct-to-consumer products. You will define microarchitecture, integrate IP, and perform RTL coding and verification to deliver high-performance hardware solutions.

The role emphasizes collaboration across hardware and software teams to push innovation while meeting energy efficiency and integration goals. In-person interviews are typical in this process, with a comprehensive compensation package

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

Responsibilities

• Define microarchitecture for a subsystem.
• Integrate internal or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation, debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

IP development experience

ASIC development (Verilog/VHDL)

Scripting: Perl or Python

Education

Bachelor's degree in EE/CE/CS or related field

Job description

Google in Mountain View is hiring for a role that focuses on designing custom silicon for our direct-to-consumer products. You will define microarchitecture, integrate IP, and perform RTL coding and verification to deliver high-performance hardware solutions.

The role emphasizes collaboration across hardware and software teams to push innovation while meeting energy efficiency and integration goals. In-person interviews are typical in this process, with a comprehensive compensation package