RTL Design Engineer, Silicon

Google LLC; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

Google LLC in Mountain View, CA is seeking a hardware-focused IC engineer to define microarchitecture and integrate IP for custom silicon powering its consumer products.

You will perform RTL coding and verification with Verilog/VHDL and collaborate across hardware, software, and AI teams to deliver high-performance, energy-efficient subsystems. The role supports comprehensive benefits and equity opportunities.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development with Verilog or VHDL.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Define microarchitecture for a subsystem.
• Integrate internal or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation, debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

IP development

Verilog

VHDL

Perl

Python

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Master's or PhD preferred (Electrical Engineering, Computer Engineering or Computer Science)

Tools

FPGA platforms

Emulation platforms

Job description

corporate_fare Google place Mountain View, CA, USA

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development withVerilogor VHDL.
• Experience with a scripting language like Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
• Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Knowledge of high-performance and energy efficient design techniques.
• Knowledge of FPGA and emulation platforms.
• Knowledge of ASIC Verification or DFT.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

• Define microarchitecture for a subsystem.
• Integrate internal or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.