Senior CPU RTL Engineer — Custom Silicon

Google LLC; Portland (OR); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a CPU Frontend Design Engineer to help shape the next generation of custom silicon powering Google’s direct-to-consumer products. You will focus on microarchitecture and RTL design, driving efficient, high‑performance hardware with cross‑team collaboration.

Ideal candidates have 8+ years in RTL, Verilog/SystemVerilog, and logic synthesis, plus a Bachelor’s degree in Electrical/Computer Engineering or Computer Science. Strong emphasis on power-aware design and integration.”

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Responsibilities

• Contribute to CPU frontend designs with emphasis on microarchitecture and RTL design.
• Propose performance-enhancing microarchitecture features and collaborate on trade-off studies.
• Communicate pros/cons of microarchitecture enhancements to enable final decisions.
• Deliver designs meeting Power, Performance and Area (PPA) goals with production quality.
• Familiarize with techniques for at least one processor functional block to guide performance modeling.

Skills

Digital logic design

RTL design concepts

Verilog/SystemVerilog

Logic synthesis

Low-power design techniques

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

Google is seeking a CPU Frontend Design Engineer to help shape the next generation of custom silicon powering Google’s direct-to-consumer products. You will focus on microarchitecture and RTL design, driving efficient, high‑performance hardware with cross‑team collaboration.

Ideal candidates have 8+ years in RTL, Verilog/SystemVerilog, and logic synthesis, plus a Bachelor’s degree in Electrical/Computer Engineering or Computer Science. Strong emphasis on power-aware design and integration.”