Senior CPU RTL Engineer – Custom Silicon Frontend

Google; Portland (OR); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Job summary

Google is seeking a senior CPU RTL design engineer to contribute to frontend designs and the next generation of microarchitecture for its custom silicon. You will collaborate with architects to evaluate performance and power trade-offs, delivering production-quality designs that meet PPA goals.

The role emphasizes experience with RTL, digital logic, and Verilog/SystemVerilog in a fast-paced, hardware-centric environment.

Qualifications

• Bachelor's degree required in Electrical/Computer Engineering, CS, or related field.
• 8+ years of experience with digital logic design, RTL design concepts, and Verilog/SystemVerilog.
• Experience with logic synthesis to optimize RTL, performance and power, including low-power techniques.

Responsibilities

• Contribute to CPU frontend designs, emphasizing microarchitecture and RTL design for the next generation CPU.
• Propose performance-enhancing microarchitecture features with efficiency in mind and study trade-offs with architects/performance teams.
• Communicate pros/cons of microarchitecture changes and assist in final decisions.
• Deliver designs meeting Power, Performance and Area goals with production quality.
• Familiarize with techniques for at least one processor functional block and translate into design constructs for performance modeling.

Skills

RTL design

Digital logic

Verilog/SystemVerilog

Education

Bachelor's degree in EE/CE/CS or equivalent

Master's or PhD preferred (computer architecture focus)

Job description

Google is seeking a senior CPU RTL design engineer to contribute to frontend designs and the next generation of microarchitecture for its custom silicon. You will collaborate with architects to evaluate performance and power trade-offs, delivering production-quality designs that meet PPA goals.

The role emphasizes experience with RTL, digital logic, and Verilog/SystemVerilog in a fast-paced, hardware-centric environment.