RTL Design Engineer, Machine Learning Accelerators

Socket.dev; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Equity

Bonus target

Job summary

Google is seeking a hardware design engineer to advance TPU architecture and accelerator technology. You will verify complex digital designs and contribute to silicon solutions powering AI/ML workloads.

The role emphasizes RTL coding in Verilog/SystemVerilog, ASIC/SoC design, and collaboration with software and architecture teams to optimize performance and power for large-scale AI systems.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 4 years of experience with custom silicon design (SoCs/ASICs).
• Experience with RTL design using Verilog or SystemVerilog.

Responsibilities

• Understand the overall application of the chip and propose improvements to the design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on interfaces and documentation.

Skills

RTL design (Verilog/SystemVerilog)

custom silicon design

Education

Bachelor's degree in EE/CE/CS or related field

Job description

Minimum qualifications:

• Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent practical experience.
• 4 years of experience with custom silicon design (e.g., SoCs, ASICs, etc.).
• Experience with RTL design using Verilog or SystemVerilog.

Preferred qualifications:

• Master's degree or PhD in electrical engineering, computer engineering, or computer science, with a focus on computer architecture.
• Experience interacting with software, architecture, and other cross-functional teams.
• Experience with a scripting language (e.g., Python or Perl).
• Experience applying engineering best practices (e.g., code review, testing, refactoring).
• Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
• Knowledge of high performance and low power design techniques.

About the job:

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Understand the overall application of the chip, proposing and developing improvements in overall design.
• Design and document one or more blocks of an ASIC, including functionality and timing.
• Work with software teams on functionality, interfaces, and documentation.