RTL Design Engineer, AI ASICs & Tapeout

Normal Computing Corporation; Palo Alto (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

Normal Computing seeks an RTL Design Engineer to own digital logic from microarchitecture to tapeout. You will craft synthesizable SystemVerilog, work with verification on debug and coverage, and partner with physical design to meet timing and area constraints.

This role emphasizes architecture decisions and close collaboration across teams. The candidate should have hands-on RTL production experience, a track record of silicon tapeouts, and comfort working where specifications are evolving in

Qualifications

• Hands-on experience writing production RTL in SystemVerilog.
• Experience delivering RTL through synthesis and place‑and‑route.
• Proven ability to close coverage and debugging across simulators and formal methods.

Responsibilities

• Write and own synthesizable RTL in SystemVerilog across datapath to memory interfaces.
• Translate high-level specs into implementable microarchitectures with architecture teams.
• Collaborate with verification to review plans and help close coverage.

Skills

RTL coding

SystemVerilog

Microarchitecture

Verification

Debugging

Collaboration

Tools

OpenTitan

Chipyard

CVA6

RISC-V

Job description

Normal Computing seeks an RTL Design Engineer to own digital logic from microarchitecture to tapeout. You will craft synthesizable SystemVerilog, work with verification on debug and coverage, and partner with physical design to meet timing and area constraints.

This role emphasizes architecture decisions and close collaboration across teams. The candidate should have hands-on RTL production experience, a track record of silicon tapeouts, and comfort working where specifications are evolving in