RTL Design Engineer

Game Seven Staffing; California (MO); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Game Seven Staffing seeks an experienced RTL Design Engineer to own blocks and subsystems on customer SoC programs. You will transform architecture into RTL, work with DV engineers, and contribute from day one on real tapeouts, with high ownership and direct impact on chip development.

The role blends traditional RTL design with AI-assisted tooling, requiring SystemVerilog expertise, clocking/timing, and collaboration with customer architects on-site when needed.

Qualifications

• 6+ years of hands-on RTL design experience with multiple production tapeouts.
• Strong SystemVerilog/Verilog skills and fluency with front-end flows (lint, CDC, synthesis, timing).
• Experience designing interconnects, switches, CPU clusters, or CPU/subsystem integration.

Responsibilities

• Own RTL design for SoC blocks and subsystems from micro-architecture through synthesis-ready RTL.
• Design and integrate interconnects, switches, and CPU clusters into customer SoCs.
• Turn architecture specs into clean interface definitions, micro-architecture docs, and implementation.
• Work with DV engineers to bring up testbenches, debug failures, and drive blocks to signoff.
• Use AI-assisted design tools throughout development and feed results back into tooling.
• Interact directly with customer architects and design leads, on-site when required.
• Find ways to optimize the design process and adopt new methodologies to shorten schedules.

Skills

RTL design

SystemVerilog/Verilog

front-end flows

interconnects/Switches/CPU clusters

AI-assisted design tools

Tools

AI tooling for design

Job description

About Us

We are developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.

Chips & Silicon

• Palo Alto Office (remote considered)
• Contract

About The Team

Backed by Silicon Valley's top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About This Role

We are building next- generation tools for silicon design by combining deep verification expertise with modern AI systems. You will be part of a silicon design team that delivers RTL for leading semiconductor companies on schedules conventional teams can't match, by pairing experienced designers with AI-driven design and verification tooling. As an RTL Design Engineer, you will own blocks and subsystems on real customer SoC programs from day one. This is hands-on design work on real tapeouts, and you will have high ownership and direct impact on real-world chip development.

What You'll Do

• Own RTL design for SoC blocks and subsystems, from micro-architecture through synthesis-ready RTL.
• Design and integrate interconnects, switches, and CPU clusters into customer SoCs.
• Turn architecture specs into clean interface definitions, micro-architecture docs, and implementation.
• Work closely with DV engineers to bring up testbenches, debug failures, and drive blocks to signoff.
• Use AI-assisted design tools throughout development, review, and debug, and feed what works back into our tooling.
• Work directly with customer architects and design leads, on-site when the program requires it.
• Find ways to optimize the design process and try new methodologies where they cut schedule.

What Makes This Role Unique

• Work on production silicon at top semiconductor companies, with AI tooling most design teams don't have yet.
• High ownership from day one, with direct customer interaction and real accountability for schedule.
• Help define how a modern, AI-native design team operates.
• Fast-moving environment built for engineers who take initiative rather than wait for direction.

Qualifications

• 6+ years of hands-on RTL design experience with multiple production tapeouts, ideally at an established semiconductor company.
• Strong SystemVerilog/Verilog skills and fluency with front-end flows (lint, CDC, synthesis, timing).
• Direct experience designing interconnects, switches, CPU clusters, or CPU/subsystem integration.
• Comfortable using AI coding and design tools as part of your daily workflow, and eager to push them further.
• Able to ramp onto a new design and contribute within days, without hand-holding.
• Fast-moving and results-driven, with a track record of shipping under tight schedules.
• Comfortable interacting directly with customer engineering teams.

Bonus Skills

• Experience with Arm CPU cluster integration or Arm-based SoC design.
• Background in Ethernet, PCIe, or high-speed networking silicon.
• Exposure to formal verification.
• Previous consulting, contract, or forward-deployed engineering experience.