RTL Design Engineer - Next-Gen Mixed-Signal ASICs

Teradyne; North Reading (MA); On-site; USD 123,000 - 197,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Retirement plan

Paid time off

Job summary

Teradyne is seeking an RTL Designer for its Silicon Technology Engineering Digital ASIC Group in North Reading, MA. You will work with Analog teams and architects on next-generation large mixed-signal ASICs from spec through silicon bringup.

You will contribute to design, verification, physical design, and bringup, using cutting-edge AI tools to optimize productivity and quality. A strong background in Verilog and high-speed memory is required.

Qualifications

• BSEE or MSEE in Electrical Engineering or related field.
• Experience writing RTL in Verilog and logic design.
• Experience with CDC, STA, timing constraints, and memory interfaces.

Responsibilities

• Develop specifications, micro-architecture, and RTL for critical blocks with the chip architect.
• Integrate industry standard and Teradyne IPs.
• Collaborate with verification for test plans and coverage to ensure first-pass silicon success.
• Provide timing constraints and STA support to Physical Design for timing closure.
• Offer post-silicon lab bringup and debugging support.

Skills

RTL design

Verilog

State machines

FIFOs

High-speed data paths

CDC

STA

Memory interfaces

Scripting (Python)

Synthesis & timing

Education

BSEE or MSEE

Job description

Teradyne is seeking an RTL Designer for its Silicon Technology Engineering Digital ASIC Group in North Reading, MA. You will work with Analog teams and architects on next-generation large mixed-signal ASICs from spec through silicon bringup.

You will contribute to design, verification, physical design, and bringup, using cutting-edge AI tools to optimize productivity and quality. A strong background in Verilog and high-speed memory is required.