Senior Digital Design Engineer

Fortune 500; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Fortune 500 is seeking a Digital Mixed-Signal Lead to steer the architecture, RTL design, and clocking IP for advanced digital control infrastructures in mixed-signal subsystems. You will own the digital logic definitions driving PLLs, FLLs, and DLLs, collaborating closely with analog and verification teams.

The role demands 8+ years in digital ASIC design, deep SystemVerilog RTL expertise, and a track record of tapeouts across advanced nodes.

Qualifications

• 8+ years of professional digital ASIC design experience.
• Deep expertise in writing robust, synthesizable SystemVerilog RTL.
• Direct experience with advanced technology nodes, specifically N5, N3P, and beyond.
• Proven history of steering cross-functional execution from initial concept through to successful tapeouts.

Responsibilities

• Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
• Design complex digital control loops, state machines for adaptive calibration, DVFS controllers, and fractional-N delta-sigma modulators.
• Serve as the primary bridge to Analog Circuit Designers and define clean boundaries at the analog-digital interface.
• Partner with Verification Teams to drive MSV and RNM strategies for high-coverage loop simulations.
• Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
• Enforce a rigorous full-chip CDC and RDC sign-off methodology for the clocking network.

Skills

Digital ASIC Design

SystemVerilog RTL

Clocking IP

Cross-functional leadership

Job description

Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems (PLLs, FLLs, and DLLs).

Core Responsibilities

• Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
• Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators.
• Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface.
• Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.
• Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
• Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network.

Candidate Requirements

• Experience: 8+ years of professional digital ASIC design experience.
• RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL
• Process Nodes: Direct experience with advanced technology nodes, specifically N5, N3P, and beyond.
• Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeouts.