Senior CPU CDC/RDC/STA Engineer — RTL & Verification

Apple Inc.; Beaverton (OR); Sur place; USD 120 000 - 150 000; Plein temps

Résumé du poste

A leading technology company is seeking a CPU CDC/RDC/STA Engineer in Beaverton, Oregon. In this role, you will develop and maintain key design sign-offs related to Clock Domain Crossing and Reset Domain Crossing for CPU designs. Ideal candidates will have at least 10 years of experience, with strong knowledge in Verilog and scripting. Join us to play a key role in delivering innovative products while collaborating closely with various teams to drive improvements and methodologies.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Experience with at least one of the following: Synopsys or Real Intent tool.
• Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations.

Responsabilités

• Developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs.
• Working with RTL and DV teams to recommend System Verilog assertions.
• Highlighting CDC/RDC issues to the RTL team and recommending solutions.

Connaissances

Clock-Domain Crossing (CDC)

Reset Domain Crossing (RDC)

Verilog

Scripting in TCL or Perl

Formation

BS degree

Outils

Synopsys

Real Intent

Spyglass

VC-Static

PrimeTime

Meridian

Description du poste

A leading technology company is seeking a CPU CDC/RDC/STA Engineer in Beaverton, Oregon. In this role, you will develop and maintain key design sign-offs related to Clock Domain Crossing and Reset Domain Crossing for CPU designs. Ideal candidates will have at least 10 years of experience, with strong knowledge in Verilog and scripting. Join us to play a key role in delivering innovative products while collaborating closely with various teams to drive improvements and methodologies.