RTL Design & FPGA Engineer

Programming.com; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Programming.com seeks an experienced FPGA/RTL engineer to develop Verilog-based synthesizable RTL, implement register maps, and drive modular RTL designs. The role emphasizes FPGA clocking structures, deterministic resets, and hands-on timing with SDC/XDC constraints.

You will work with AXI4/AXI-Lite, PCIe, I2C, SPI, UART interfaces, and leverage toolchains like VCS/Questa/ModelSim and Vivado/Lattice as needed. Lab bring-up and hardware debugging are part of the job.

Qualifications

• Verilog RTL expertise required for synthesizable designs.
• Proficiency in modular RTL design and register maps.
• Strong FPGA clocking and deterministic reset knowledge.
• Experience creating SDC/XDC timing constraints including clock definitions and IO delays.
• Hands-on with FPGA I/O pin planning and device bank rules.
• Proficient in Makefile and Tcl-based build automation.
• Experience with Verilog/SystemVerilog simulations (VCS/Questa/ModelSim/Vivado).
• Experience with embedded FPGA debug tools (ILA, SignalTap, ChipScope).
• Lab board bring-up, PLD programming, and hardware debugging experience.
• Familiarity with protocols such as AXI4/AXI-Lite, AHB-Lite, APB, PCIe, I2C, SPI, MDIO, UART.
• Experience with Quartus or Lattice toolchains is a plus.

Skills

Verilog RTL

RTL design

register map

modular RTL

FPGA clocking

deterministic resets

SDC/XDC timing

timing constraints

I/O planning

device banks

Makefile

Tcl scripting

Verilog/SystemVerilog sim

VCS/Questa/ModelSim/Vivado

lab board bring-up

hardware debugging

AXI4/AXI-Lite/AHB-Lite/APB

PCIe/I2C/SPI/MDIO/UART

Quartus/Lattice

Tools

FPGA toolchains

VCS

Questa/ModelSim

Vivado Simulator

Quartus

Lattice tools

Job description

The ideal candidate should have proven expertise in Verilog-based synthesizable RTL

development, register map implementation, and modular RTL design. Strong experience with

Strong experience with FPGA clocking structures and deterministic reset schemes is required.

Required experience includes:

• Proven Verilog expertise in synthesizable RTL, register map implementation, and modular design.
• Strong understanding of FPGA clocking structures and deterministic reset schemes.
• Experience with at least one of the following FPGA toolchains:
• Hands-on experience writing SDC/XDC timing constraints, including clock definitions, I/O delays, and timing exceptions.
• Experience with FPGA I/O pin planning and device bank rules.
• Experience developing Makefile and/or Tcl-based build automation.
• Experience with Verilog and/or SystemVerilog simulation using tools such as VCS, Questa/ModelSim, or Vivado Simulator.
• Experience with embedded FPGA debug tools such as ILA, SignalTap, or ChipScope.
• Hands-on experience with lab board bring-up, PLD programming, and hardware debugging.
• Working experience with some standard protocols, such as AXI4/AXI-Lite, AHB-Lite, APB, PCIe, I2C, SPI, MDIO, or UART. Experience with all listed protocols is not required.
• Experience with Quartus or Lattice toolchains would be a plus.