Senior CDC/RDC RTL Design Engineer for SoC

ZealHire Inc.; San Jose, Northern (CA, KY); Hybrid; USD 150,000 - 190,000; Full time

Job summary

ZealHire Inc. is seeking an experienced CDC/RDC Engineer to advance verification and signoff on complex SoC designs focused on clock-domain and reset-domain crossing issues.

The role involves developing constraints and methodologies, debugging metastability risks, and collaborating with RTL, Design, Physical Design, and Verification teams to resolve issues. Candidates should have strong Verilog/SystemVerilog skills and experience with SpyGlass/Questa tools.

Qualifications

• Experience performing CDC/RDC analysis and signoff on SoC designs.
• Strong RTL knowledge in Verilog/SystemVerilog and clock/reset architectures.
• Experience with CDC/RDC tools (SpyGlass, Questa, or Cadence).

Responsibilities

• Perform CDC and RDC analysis, verification, and signoff for complex SoC designs.
• Develop and review CDC/RDC constraints, waivers, and methodologies.
• Analyze and debug clock-domain and reset-domain crossing violations.
• Collaborate with RTL, Design, Physical Design, and Verification teams to resolve issues.
• Review RTL for proper clock/reset synchronization and identify metastability risks.
• Run CDC/RDC checks and generate detailed reports for design reviews and signoff.
• Support methodology development, automation, and scripting using Tcl/Python where required.
• Participate in design reviews and ensure CDC/RDC quality across multiple IPs and SoC blocks.

Skills

CDC/RDC verification

Verilog/SystemVerilog

Clock Domain Crossing

Debugging

Tcl/Python scripting

Tools

SpyGlass CDC

VC SpyGlass

Questa CDC

Cadence tools

Job description

ZealHire Inc. is seeking an experienced CDC/RDC Engineer to advance verification and signoff on complex SoC designs focused on clock-domain and reset-domain crossing issues.

The role involves developing constraints and methodologies, debugging metastability risks, and collaborating with RTL, Design, Physical Design, and Verification teams to resolve issues. Candidates should have strong Verilog/SystemVerilog skills and experience with SpyGlass/Questa tools.