RTL Design Architect – Ultra-Low-Power Edge SoC

Efficient Computer; San Jose (CA); On-site; USD 160,000 - 250,000; Full time

Benefits offered by this job

401K match

Equity program

Paid parental leave

Flexible work

Company-paid benefits

Job summary

Efficient is seeking a Lead RTL Design Engineer to own the microarchitecture and RTL implementation across dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, and low-power logic for a power-efficient edge/IoT SoC.

You will collaborate with architects, DV leads, physical design, and firmware teams to tape out an industry-leading, energy-conscious processor. This is a unique chance to influence the hardware stack as we move toward production and scale.

Qualifications

• 8+ years of RTL design with tape-out ownership of dataflow based design, on-chip networks, memory subsystems or peripheral integration
• Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware
• Familiarity with dataflow, SIMD, or systolic array architectures and token-based synchronization
• Experience with on-chip memory design and low-power RTL techniques (UPF, clock gating, power domains)
• Experience with bus protocols (AXI/AHB/APB/TileLink) at RTL level
• Strong ability to read/write SDC constraints and timing reports

Responsibilities

• Own microarchitecture definition for core compute units and dataflow pipelines
• Define and drive on-chip interconnects and data movement across the fabric
• Define memory subsystem interfaces, data movement and synchronization behavior
• Lead configuration, scheduling, and execution of workloads on the fabric (multi-kernel)
• Drive power architecture across the design (clocking, resets, power domains)
• Collaborate with compiler/software teams to map workloads efficiently to hardware
• Mentor RTL engineers, review RTL, and enforce coding standards
• Support silicon bring-up with scan/DFT guidelines and RTL-level debugging

Skills

RTL design

SystemVerilog

Dataflow architectures

Memory subsystems

Power/low-power RTL

Synthesis and timing

Tools

AXI/NoC protocols

Job description

Efficient is seeking a Lead RTL Design Engineer to own the microarchitecture and RTL implementation across dataflow execution fabric, memory subsystem, on-chip interconnect/NoC, and low-power logic for a power-efficient edge/IoT SoC.

You will collaborate with architects, DV leads, physical design, and firmware teams to tape out an industry-leading, energy-conscious processor. This is a unique chance to influence the hardware stack as we move toward production and scale.