RTL Design Lead: NoC & High-Speed Interconnect

Architect; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Architect Labs in Palo Alto seeks an experienced RTL design lead to own the AI-driven fabric for production silicon. You will define NoC routers, crossbar switches, and PCIe/CXL bridges to deliver low-latency, high-bandwidth interconnects across ML accelerators.

You will collaborate with DV, SW, and ML teams to refine microarchitectural specs and validate fabric configurations on FPGA platforms, balancing area, timing, and power across the SOC.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
• Deep familiarity with ARM AMBA protocol suite — AXI4/AXI5 (channel mechanics, burst types, ordering, exclusive access), ACE/ACE-Lite (coherence transactions, snoop channels), CHI (request/response/data/snoop flits, home nodes, snoop filters), and legacy AHB/APB for peripheral integration.
• Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects including arbitration schemes (round-robin, priority, age-based, bandwidth-regulated), virtual channel management, flow control (credit-based, ready/valid), and QoS mechanisms.
• Experience with HSIO bridge logic — PCIe root complex/endpoint bridge design, CXL.io/CXL.mem/CXL.cache protocol translation, or custom chip-to-chip links (UCIe, proprietary die-to-die) including link-layer protocols, credit management, and replay/retry logic.
• Experience with peer-to-peer DMA architectures, zero-copy data transfer engines, scatter-gather descriptors, and direct device-to-device communication paths that bypass host memory bottlenecks.
• Clear, synthesizable SystemVerilog RTL with strong design habits — parameterization for configurable port counts and data widths, modularity for hierarchical fabric composition, and configurability for different topology and QoS instantiations.
• Solid grasp of synthesis, timing constraints (especially for wide crossbar paths and high-radix switches), clock domain crossings, reset strategies, and power management for interconnect logic.
• Python: design automation, traffic generation/analysis, NoC configuration scripting, regression infrastructure.
• PPA Ownership: experience taking an interconnect or fabric block from RTL through synthesis and working with PD teams on timing/area/power closure — particularly for wide-datapath crossbars and high-frequency router pipelines.
• Bonus: Coherent multi-chip/multi-die interconnect architectures (chiplet-based designs, UCIe).
• Bonus: Knowledge of MOESI/MESIF cache-coherence protocols and snoop-filter design.
• Bonus: FPGA prototyping experience (Xilinx Vivado/Vitis) with AXI interconnect IPs and NoC IPs.

Responsibilities

• Own the on-chip fabric RTL end-to-end: NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure.
• Design and implement AMBA-based interconnect fabrics: AXI/ACE/CHI crossbar switches and NIs, and protocol converters.
• Architect NoC routers and topologies: virtual-channel routers, wormhole switching, adaptive routing, QoS arbitration, deadlock-free design.
• Design high-speed I/O fabric bridges and peer-to-peer engines: PCIe/CXL bridges, die-to-die links, and peer DMA controllers.
• Collaborate with the principal architect to refine microarchitectural specs and balance latency, bandwidth, area, and power.
• Define and maintain interface specifications: AMBA AXI4/AXI5, ACE/ACE-Lite, CHI, AXI-Stream, and high-speed SerDes interfaces.
• Build and maintain RTL infrastructure for in-house AI-driven flow: scripts, NoC config generators, regression, lint/CDC waivers.
• Work with DV teams to verify interconnect models, protocol monitors, SVA assertions, and coverage for edge-case traffic.
• Collaborate with SW and ML teams to optimize fabric configurations for ML workloads and traffic patterns.
• Support FPGA prototyping on Xilinx platforms for early functional validation of the fabric.

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field

Tools

SystemVerilog

Job description

Architect Labs in Palo Alto seeks an experienced RTL design lead to own the AI-driven fabric for production silicon. You will define NoC routers, crossbar switches, and PCIe/CXL bridges to deliver low-latency, high-bandwidth interconnects across ML accelerators.

You will collaborate with DV, SW, and ML teams to refine microarchitectural specs and validate fabric configurations on FPGA platforms, balancing area, timing, and power across the SOC.