RTL Power Architect for SoC Efficiency

Advanced Micro Devices; Austin, Northern (TX, KY); Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

Hybrid work model

AMD benefits

Job summary

Advanced Micro Devices seeks an RTL Power Design Specialist to join the Security IP (SECIP) design team. You will define IP power specs, drive power targets, and work with IP, SoC, and methodology teams to optimize power while preserving performance.

The ideal candidate has strong Verilog/SystemVerilog skills, power-aware design experience, and the ability to lead and mentor in a collaborative environment. This hybrid Austin, TX role offers challenging projects and growth opportunities.

Qualifications

• Bachelor's, Master's, or Ph.D. in Electrical/Computer Engineering, CS, or related field.
• Proficiency in Verilog/SystemVerilog; strong RTL power design knowledge.
• Experience with ASIC design/verification tools and power-aware flows.
• Knowledge of power measurement methodologies and tissue for IP/SoC power targets.

Responsibilities

• Develop and maintain RTL IP power specs aligned with SoC power requirements.
• Define and track IP power targets; identify optimization opportunities.
• Collaborate with verification to develop power vectors for simulations.
• Develop and maintain power regression infrastructure and analyze results.
• Adopt advanced power architectures and methodologies to meet SoC power targets.
• Contribute to corporate power methodology and influence IP power strategy.
• Provide technical leadership and mentor team members.

Skills

Verilog/SystemVerilog

Scripting languages

RTL power architecture

Cross-functional collaboration

Education

Bachelor's, Master's or Ph.D. in Electrical Engineering/Computer Engineering/Computer Science

Tools

RTL simulation

Linting

Synthesis

Power-aware verification

Job description

Advanced Micro Devices seeks an RTL Power Design Specialist to join the Security IP (SECIP) design team. You will define IP power specs, drive power targets, and work with IP, SoC, and methodology teams to optimize power while preserving performance.

The ideal candidate has strong Verilog/SystemVerilog skills, power-aware design experience, and the ability to lead and mentor in a collaborative environment. This hybrid Austin, TX role offers challenging projects and growth opportunities.