RISC‑V CPU Verification Engineer — Lead Verification & Validation
Qualcomm
Santa Clara (CA)
On-site
USD 167,100 - 250,700
Full time
14 days+
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Benefits offered by this job
Annual discretionary bonus
Competitive benefits package
Opportunities for RSU grants
Job summary
A leading technology company in Santa Clara, California is seeking a Design Verification Engineer to validate CPU and SOC micro-architectures. The ideal candidate will develop detailed test plans and verification methodologies, ensuring the designs meet launch readiness standards. Applicants should have extensive knowledge of RISC-V architecture and experience leading verification teams. This position offers competitive compensation in addition to an annual discretionary bonus and RSU grants as part of a comprehensive benefits package.
Qualifications
Extensive knowledge of industry Instruction Set Architectures, particularly RISC-V.
Deep knowledge of Micro-Processor Verification functions.
Experience in leading a small team of Verification engineers.
Responsibilities
Validate CPU and SOC level micro-architectures.
Develop Verification Plans and Testbenches.
Execute Verification Plans and Debug test failures.
Skills
RISC-V architecture
Micro-Processor Verification
Random Instruction Sequencing
Formal verification techniques
Assembly code writing
Education
BS in Computer Engineering
MS in Electrical Engineering
PhD in related field
Tools
Simulators
Mixed signal Verification tools
Waveform viewers
Job description
A leading technology company in Santa Clara, California is seeking a Design Verification Engineer to validate CPU and SOC micro-architectures. The ideal candidate will develop detailed test plans and verification methodologies, ensuring the designs meet launch readiness standards. Applicants should have extensive knowledge of RISC-V architecture and experience leading verification teams. This position offers competitive compensation in addition to an annual discretionary bonus and RSU grants as part of a comprehensive benefits package.