RISC-V SoC Verification Architect — Remote Lead

JDWK; Austin (TX); Hybrid; USD 140,000 - 230,000; Full time

Benefits offered by this job

Ownership of verification strategy

Remote-friendly startup

Job summary

JDWK Inc. is building a fast-moving hardware team focused on RISC-V based SoCs. We seek a Design Verification Engineer to own the verification environment and drive scalable testbench automation across RTL and firmware layers.

You will develop constrained-random and coverage-driven tests, integrate CI/CD, and collaborate with RTL, FPGA, and software teams to ensure comprehensive system-level verification across simulation and prototyping platforms.

Qualifications

• 5+ years of experience in ASIC/SoC design verification.
• Strong proficiency in SystemVerilog/UVM or equivalent.
• Hands-on experience verifying RISC-V cores, memory subsystems, and interconnects.
• Experience developing regression and CI flows (Jenkins, GitLab CI).
• Proficiency in scripting (Python, Tcl, shell).
• Knowledge of FPGA-based verification and bring-up.
• Understanding of software-based validation (firmware/bare-metal).
• Strong analytical and debugging skills; startup-friendly.

Responsibilities

• Own the verification environment for the RISC‑V CPU and SoC, from architecture to execution.
• Develop and maintain testbench infrastructure for block and SoC verification.
• Design constrained-random, directed, and coverage-driven tests.
• Integrate verification flows into CI/CD pipelines for regression testing.
• Collaborate with design engineers to implement checkers and assertions.
• Monitor verification coverage metrics and drive closure.
• Leverage FPGA prototyping for accelerated testing and validation.
• Collaborate with software and systems teams to develop test firmware.

Skills

SystemVerilog/UVM

RISC-V verification

CI/CD automation

Python scripting

Debugging

Tools

VCS

Xcelium

Questa

Verilator

QEMU

Job description

JDWK Inc. is building a fast-moving hardware team focused on RISC-V based SoCs. We seek a Design Verification Engineer to own the verification environment and drive scalable testbench automation across RTL and firmware layers.

You will develop constrained-random and coverage-driven tests, integrate CI/CD, and collaborate with RTL, FPGA, and software teams to ensure comprehensive system-level verification across simulation and prototyping platforms.