RISC-V CPU Architect & RTL Lead

JDWK Inc.; United States; Remote; USD 225,000 - 300,000; Full time

Job summary

JDWK Inc. is seeking a hands-on CPU RTL Lead to own RISC-V core development, from architecture through RTL implementation.

You will evaluate open-source cores and design enhancements for our custom silicon roadmap while leading verification, synthesis, and performance analysis flows in a fast-paced startup. You will collaborate with SoC, memory, and firmware teams to ensure seamless integration and coding standards.

Qualifications

• 7+ years of RTL design experience on CPU or DSP projects.
• Deep understanding of CPU microarchitecture, pipelines, hazards, caches and MMUs.
• Strong knowledge of the RISC-V ISA and extensions.
• Hands-on with open-source RISC-V cores such as Rocket, CVA6, Ibex or BOOM.
• Proficiency in SystemVerilog/Verilog RTL design, simulation and synthesis.
• Experience with EDA tools for synthesis and linting.
• Solid verification experience (UVM, formal or constrained-random).
• Strong communication and cross-functional collaboration.

Responsibilities

• Own the RISC-V CPU microarchitecture and RTL implementation.
• Evaluate and compare open-source RISC-V cores.
• Architect enhancements or new cores for specific domains.
• Develop and maintain high-quality, synthesizable RTL.
• Define verification strategy with UVM, formal or FPGA-based validation.
• Optimize for PPA targets through microarchitectural tuning.
• Collaborate with SoC, memory, and firmware teams for integration.
• Establish coding standards, linting, and CI for RTL and verification.
• Mentor engineers and help build a small design team.

Skills

RTL design

CPU microarchitecture

RISC-V ISA

Open-source RISC-V

SystemVerilog

EDA tools

Verification methods

Cross-functional

Startup mindset

Mentoring

Tools

Synopsys

Cadence

Open-source flows

Job description

JDWK Inc. is seeking a hands-on CPU RTL Lead to own RISC-V core development, from architecture through RTL implementation.

You will evaluate open-source cores and design enhancements for our custom silicon roadmap while leading verification, synthesis, and performance analysis flows in a fast-paced startup. You will collaborate with SoC, memory, and firmware teams to ensure seamless integration and coding standards.