Staff CPU RTL Design Engineer - RISC-V Core & MMU

SiFive, Inc.; Santa Clara (CA); On-site; USD 178,848 - 218,592; Full time

Benefits offered by this job

Healthcare and retirement plans

Paid time off

Equity options

Job summary

SiFive, Inc. is seeking a Staff RTL Design Engineer to join their team in Santa Clara, California. You will work on designing CPU cores based on RISC-V architecture, contributing to cutting-edge hardware developments.

The ideal candidate should have a BS/MS in engineering, at least 3 years of design experience, and proficiency in RTL design languages like Verilog or System Verilog. SiFive offers competitive pay, incentives, and a comprehensive benefits package.

Qualifications

• 3+ years of design experience in CPU RTL design.
• Proficient in hardware design with Verilog/System Verilog/VHDL.
• Strong software engineering skills, particularly in test-driven development.

Responsibilities

• Architect and implement features and performance improvements in RISC-V CPU cores.
• Collaborate with verification and implementation teams for quality assurance.
• Document knowledge and participate in collaborative design.

Skills

Verilog/System Verilog/VHDL

Object-oriented programming

Attention to detail

Team collaboration

Education

BS/MS degree in computer science, computer engineering, electrical engineering or related field

Tools

Git/Github

Jira

Confluence

Job description

SiFive, Inc. is seeking a Staff RTL Design Engineer to join their team in Santa Clara, California. You will work on designing CPU cores based on RISC-V architecture, contributing to cutting-edge hardware developments.

The ideal candidate should have a BS/MS in engineering, at least 3 years of design experience, and proficiency in RTL design languages like Verilog or System Verilog. SiFive offers competitive pay, incentives, and a comprehensive benefits package.