RISC‑V CPU Performance Verification Engineer

Georgian; Austin (TX); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a talented engineer to join the CPU design team to drive performance verification and RTL-to-model correlation for a high-performance RISC-V-based CPU.

The role is hybrid, based out of Austin, TX or Santa Clara, CA, with collaboration across core architects and RTL teams to deliver an efficient design and validated performance metrics. Open to multiple seniorities and compensated accordingly.

Qualifications

• Experience analyzing modern CPU performance data and bottlenecks.
• Proficient in C++ and Python; familiar with compilation, simulation, and emulation tools.
• Knowledge of high-performance CPU core architecture and RTL/debugging.

Responsibilities

• Join a team driving improvements in CPU microarchitecture, verify performance and correlate RTL against the performance model.
• Draft performance test plans and develop microbenchmarks to exercise features and expose bottlenecks.
• Enhance tools/methodologies for performance analysis and correlation to improve development efficiency.

Skills

C++

Python

RTL debugging

Performance modeling

CPU architecture

Debugging pre-silicon

Job description

Tenstorrent is seeking a talented engineer to join the CPU design team to drive performance verification and RTL-to-model correlation for a high-performance RISC-V-based CPU.

The role is hybrid, based out of Austin, TX or Santa Clara, CA, with collaboration across core architects and RTL teams to deliver an efficient design and validated performance metrics. Open to multiple seniorities and compensated accordingly.